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arXiv:2212.00337

Fault Models in Superconducting quantum circuits

Qifan Huang, Boxi Li, Minbo Gao, Mingsheng Ying

Published Dec 1, 2022• 1 citation
arXivHTMLPDF

Abstract

Fault models are indispensable for many EDA tasks, so as for design and implementation of quantum hardware. In this article, we propose a fault model for superconducting quantum systems. Our fault model reflects the real fault behavior in control signals and structure of quantum systems. Based on it, we conduct fault simulation on controlled-Z gate and quantum circuits by QuTiP. We provide fidelity benchmarks for incoherent faults and test patterns of minimal test repetitions for coherent faults. Results show that with 34 test repetitions a 10% control noise can be detected, which help to save test time and memory.

DOI
10.48550/arxiv.2212.00337

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•Aug 19, 2013•1 citation
Fault models are indispensable for many EDA tasks, so as for design and implementation of quantum hardware. In this article, we propose a fault model for superconducting quantum systems. Our fault model reflects the real fault behavior in control signals and structure of quantum systems. Based on it, we conduct fault simulation on controlled-Z gate and quantum circuits by QuTiP. We provide fidelity benchmarks for incoherent faults and test patterns of minimal test repetitions for coherent faults. Results show that with 34 test repetitions a 10% control noise can be detected, which help to save test time and memory.
Testing for quantum circuits (QC) is a challenging task because QC is intrinsically probabilistic. Existing fault models for QC, such as missing gate faults, are not suitable for quantum dot QC. This paper proposes realistic fault models and fault simulation for quantum dot QC. Our fault models are based on real physical phenomenon of quantum dot devices so that they represent real defect behavior or control errors. Our fault simulation does not need to fully expand gate matrices to 2nx 2n, where n is the number of qubits. Using sparse matrix multiplication, our fault simulation saves a lot of memory and CPU time. We also calculate the test repetition of each test pattern so that we can estimate our test time. Based on fault simulation of a full adder QC, we can select a small test set of six test patterns, totally 526 repetitions, to detect all faults with 99% confidence level.
Detection and isolation of faults is a crucial step in the physical realization of quantum circuits. Even though quantum gates and circuits compute reversible functions, the standard techniques of automatic test pattern generation (ATPG) for classical reversible circuits are not directly applicable to quantum circuits. For faulty quantum circuits under the widely accepted single fault assumption, we show that their behavior can be fully characterized by the (single) faulty gate and the corresponding fault model. This allows us to efficiently determine test input states as well as measurement strategy for fault detection and diagnosis. Building on top of these, we design randomized algorithms which are able to detect every nontrivial single-gate fault with minimal probability of error. We also describe similar algorithms for fault diagnosis. We evaluate our algorithms by the number of output samples that needs to be collected and the probability of error. Both of these can be related to the eigenvalues of the operators corresponding to the circuit gates. We experimentally compare all our strategies with the state-of-the-art ATPG techniques for quantum circuits under the “single missing faulty gate” model and demonstrate that significant improvement is possible if we can exploit the quantum nature of circuits.
This research paper provides an in-depth examination of verification and testing approaches for quantum circuits, focusing on methodologies essential for ensuring the correctness, reliability and operational efficiency of quantum computing systems. Since quantum circuits function on the fundamental principles of superposition and entanglement, they present verification challenges that cannot be effectively addressed using conventional classical testing techniques. As a result, the development of specialized quantum-specific verification strategies has become critically important. The study highlights simulation-based verification as a foundational technique, wherein the outcomes of quantum circuit simulations are systematically compared with results obtained from physical quantum hardware. This process enables the identification of functional inconsistencies and supports iterative refinement of circuit designs. In addition, randomized benchmarking is examined as a key evaluation method for estimating circuit fidelity and quantifying error rates through the application of random gate sequences and performance comparisons against established benchmarks. To further improve system robustness, the research investigates fault-tolerant mechanisms, particularly quantum error correction codes, which play a vital role in minimizing the effects of noise, decoherence and hardware imperfections. The integration of advanced quantum metrology and characterization techniques is also explored, enabling precise measurement and detailed analysis of quantum system behavior. These techniques provide deeper insights into circuit performance and contribute significantly to validation processes. By combining simulation-based verification, randomized benchmarking, fault-tolerant protocols and quantum metrology, this study proposes a comprehensive and reliable framework for quantum circuit verification and testing. The findings contribute to the advancement of dependable quantum technologies and support their growing applications in areas such as cryptography, materials science and other emerging domains.
This paper introduces the problem of test generation and test minimization for quantum circuits using a discrete fault model. QuFault, our software package generates test sequences for arbitrary quantum circuits using the very efficient simulator QuIDDPro [1]. The quantum fault table and the test set minimization algorithm is presented, along with some tricks to make quantum testing as deterministic as possible. As our fault model we use the single qubit rotation operators about the x, y and z axis. The angle of the rotation is based on the expected accuracy of the mechanism performing the unitary operations, or the largest impact of expected noise from the environment. We consider superposition inputs as well as interference in order to detect phase faults, such as possible errors traveling backwards through controlled gates.
Detecting and isolating faults is crucial for synthesis of quantum circuits. Under the single fault assumption that is now routinely accepted in circuit fault analysis, we show that the behaviour of faulty quantum circuits can be fully characterized by the single faulty gate and the corresponding fault model. This allows us to efficiently determine test input states as well as measurement strategy that can be used to detect every single-gate fault using very few test cases and with minimal probability of error; in fact we demonstrate that most commonly used quantum gates can be isolated without any error under the single missing gate fault (SMGF) model. We crucially exploit the quantum nature of circuits to show vast improvement upon the existing works of automatic test pattern generation (ATPG) for quantum circuits.
Abstract-Quantum theory of computation establishes that there are problems for which quantum algorithms are far more efficient than their classical counterpart. Advances in quantum computing have initiated the design of systems based on quantum logic gates. Quantum computer hardware being primarily available in research laboratories at present, it mandates the ability to design, develop and test quantum logic operations by simulation of quantum logic circuits on classical computers. In this paper, we have defined a programming model for the design of a quantum circuit simulator, which can simulate a given quantum circuit obeying the rules of quantum gate operations. The quantum gate operations on both pure and superposed quantum states are being done with the help of effective data structures. The proposed quantum circuit simulator also incorporates the simulation of quantum circuit error under the action of certain quantum faults.