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Design of A Hardware Description Language Based Quantum Circuit Simulator

Amlan Chakrabarti, Susmita Sur‐Kolay, Sudhindu Bikash Mandal

Published Aug 19, 2013• 1 citation
OpenAlex

Abstract

Abstract-Quantum theory of computation establishes that there are problems for which quantum algorithms are far more efficient than their classical counterpart. Advances in quantum computing have initiated the design of systems based on quantum logic gates. Quantum computer hardware being primarily available in research laboratories at present, it mandates the ability to design, develop and test quantum logic operations by simulation of quantum logic circuits on classical computers. In this paper, we have defined a programming model for the design of a quantum circuit simulator, which can simulate a given quantum circuit obeying the rules of quantum gate operations. The quantum gate operations on both pure and superposed quantum states are being done with the help of effective data structures. The proposed quantum circuit simulator also incorporates the simulation of quantum circuit error under the action of certain quantum faults.

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Abstract-Quantum theory of computation establishes that there are problems for which quantum algorithms are far more efficient than their classical counterpart. Advances in quantum computing have initiated the design of systems based on quantum logic gates. Quantum computer hardware being primarily available in research laboratories at present, it mandates the ability to design, develop and test quantum logic operations by simulation of quantum logic circuits on classical computers. In this paper, we have defined a programming model for the design of a quantum circuit simulator, which can simulate a given quantum circuit obeying the rules of quantum gate operations. The quantum gate operations on both pure and superposed quantum states are being done with the help of effective data structures. The proposed quantum circuit simulator also incorporates the simulation of quantum circuit error under the action of certain quantum faults.
Work is in progress throughout the globe to efficiently use the potential of the quantum theory of computation over their classical counterpart and hence there is a need of building quantum computing hardware. The target of building quantum computers can be achieved if we have better tools for the design of quantum hardware. Quantum circuit simulators are tools for the logic verification of quantum circuits and they can be an essential component of quantum CAD tools in the future. This work is the extension of the previous work by the authors, in order to increase the efficiency of the simulator and to incorporate more components in the gate library. In this paper we have proposed an efficient simulator which can simulate a quantum circuit specified using the proposed quantum hardware descriptive language (QHDL).
The quantum algorithms could efficiently solve problems having exponential classical solutions [8]. The circuit model is considered as the most feasible implementation of the quantum algorithms [17]. This paper tries to find common ground between classical circuit design techniques and quantum computation, by identifying quantum circuit specification and simulation tools under the form of Hardware Description Languages (HDLs). The HDL-based simulation approach could reduce the complexity of quantum circuit simulation, by considering entanglement as the main source of gate-level simulation complexity, and isolating it in an automated manner. This is possible by taking advantage of the HDL feature of describing a circuit with both structural and functional architectures. We also performed an analysis of our methodology effectiveness, for the arithmetic circuits involved in Shor's algorithm and the circuits implementing Grover's algorithm. Our method is further improved by an entangled representation avoidance technique called 'bubble logic insertion'.
Quantum-mechanical phenomena are playing an increasing role in information processing as transistor sizes approach the nanometer level, while the securest forms of communication rely on quantum data encoding. When they involve a finite number of basis states, these phenomena can be modeled as quantum circuits, the quantum analogue of conventional or classical logic circuits. Simulation of quantum circuits can therefore be used as a tool to evaluate issues in the design of quantum information processors. Unfortunately, simulating such phenomena efficiently is exceedingly difficult. The matrices representing quantum operators (gates) and vectors modeling quantum states grow exponentially with the number of quantum bits. The information represented by quantum states and operators often exhibits structure that can be exploited when simulating certain classes of quantum circuits. We study the development of simulation methods that run on classical computers and take advantage of such repetitions and redundancies. In particular, we define a new data structure for simulating quantum circuits called the quantum information decision diagram (QuIDD). A QuIDD is a compressed graph representation of a vector or matrix and permits computations to be performed directly on the compressed data. We develop a comprehensive set of algorithms for operating on QuIDDs in both the state-vector and density-matrix formats, and evaluate their complexity. These algorithms have been implemented in a general-purpose simulator program for quantum-mechanical applications called QuIDDPro. Through extensive experiments conducted on representative quantum simulation applications, including Grover's search algorithm, error characterization, and reversible circuits, we demonstrate that QuIDDPro is faster than other existing quantum-mechanical simulators such as the National Institute of Standards and Technology's QCSim program, and is far more memory-efficient. Using QuIDDPro, we explore the advantages of quantum computation over classical computation, simulate quantum errors and error correction, and study the impact of numerical precision on the fidelity of simulations. We also develop several novel algorithms for testing quantum circuit equivalence and compare them empirically. The QuIDDPro software is equipped with a user-friendly interface and is distributed with numerous example scripts. It has been used as a laboratory supplement for quantum computing courses at several universities.
This paper addresses the problem of evaluating the fault tolerance algorithms and methodologies (FTAMS) designed for quantum circuits, by making use of fault injection techniques. These techniques are inspired from their rich classical counterparts, and were adapted to the quantum computation specific features, including the available error models. Because of their wide spectrum of application, including quantum circuit simulation, and their flexibility in circuit representation (i.e. both behavioral and structural descriptions of a circuit are possible), the hardware description languages (HDLs) appear as the best choice for our simulation experiments. The techniques employed for fault injection are based on simulator commands. The simulation results for the fault-affected circuit were compared to the outputs of a Gold circuit (a faultless circuit) in order to compute the quantum failure rate.
Recently quantum computing has achieved significant results both in theoretical and experimental areas and quantum algorithms have drawn the attention of many scientists. At the present there exist several experiments that realized some parts of certain important quantum algorithms. While those experiments work with only up to seven qubits, quantum simulators allow scientists to design algorithms with many more qubits. The existing simulators have one or more of the following restrictions: either they require powerful computers and additional computation packages such as Matlab or Mathematica or they don't provide an easy method for interacting between the classical and quantum parts of an algorithm. More importantly, none of them can simulate a generic 64-qubit circuit. It is important at this stage of quantum computing development to investigate technological improvements in simulating quantum circuit design. In this thesis we developed a specialized data structure, QSV, for quantum simulators along with new method for calculation of the new state vector after application of a quantum gate in a quantum simulator. We also developed a technique that speeds up the simulation time with our QSV vectors. With those results we built a quantum simulator that overcomes many shortcomings in other simulators and it has many advanced features. Our simulator can simulate many 64-qubit circuits and it can directly simulate multiple qubit gates as well as allows users to define gates with up to 10 qubits. The simulation time is much less in comparison with other simulators we tested. The simulator defines specifications so that users can easily design and test quantum circuits. With the simulator we also developed some new quantum circuits and verified many designs and constructions.
Quantum computing emulators are widely used for testing quantum algorithms ideally before executing them on real quantum processors. Therefore, researchers are very active in developing emulators primarily on FPGAs. This project is complex and requires a long time and a specific expertise if carried out following the low-level design approach using a Hardware Description Language (HDL). This paper describes, step by step, the process of quick designing a quantum gate emulator using a much simpler high-level design approach. It begins with the development of a quantum gate simulator in the MATLAB® environment, and subsequently translates it into an HDL design for FPGA implementation by using the MATLAB’s HDL Coder toolbox. However, while code translation may seem straightforward using MATLAB toolboxes, it becomes a non-trivial task when transitioning from a quantum computing simulator to an HDL-based quantum computing emulator. Thus, it was necessary to conduct an in-depth study to implement a quantum computing simulator in MATLAB, enabling an error-free translation of HDL code. The developed method enables the designer to leverage the highly useful and straightforward model-based design approach offered by MATLAB, rather than directly the more complex HDL approach, returning a highly optimized HDL code for configuring the FPGA as a quantum computing emulator. This topic makes the design of quantum emulators on FPGA quick, reliable, optimized and without the need for specialized hardware design skills. Additionally, two implementation examples have been described using Intel FPGA on development boards DE1_SoC and DE5a-NET DDR4 provided by Terasic Inc.