ACM/IEEE Design Automation Conference (DAC)

Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits

Cheng-Yun Hsieh, Chen-Hung Wu, Chia-Hsien Huang, His-Sheng Goan, James Chien Mo Li

Published Jul 1, 2020• 2 citations

Abstract

Testing for quantum circuits (QC) is a challenging task because QC is intrinsically probabilistic. Existing fault models for QC, such as missing gate faults, are not suitable for quantum dot QC. This paper proposes realistic fault models and fault simulation for quantum dot QC. Our fault models are based on real physical phenomenon of quantum dot devices so that they represent real defect behavior or control errors. Our fault simulation does not need to fully expand gate matrices to 2nx 2n, where n is the number of qubits. Using sparse matrix multiplication, our fault simulation saves a lot of memory and CPU time. We also calculate the test repetition of each test pattern so that we can estimate our test time. Based on fault simulation of a full adder QC, we can select a small test set of six test patterns, totally 526 repetitions, to detect all faults with 99% confidence level.

DOI: 10.1109/dac18072.2020.9218573

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