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arXiv:2207.05568 · Quantum Science and Technology

Benchmarking quantum error-correcting codes on quasi-linear and central-spin processors

Regina Finsterhoelzl, Guido Burkard

Published Nov 11, 2022• 8 citations
arXivHTMLPDF

Abstract

Abstract We evaluate the performance of small error-correcting codes, which we tailor to hardware platforms of very different connectivity and coherence: on a superconducting processor based on transmon qubits and a spintronic quantum register consisting of a nitrogen-vacancy center in diamond. Taking the hardware-specific errors and connectivity into account, we investigate the dependence of the resulting logical error rate on the platform features such as the native gates, native connectivity, gate times, and coherence times. Using a standard error model parameterized for the given hardware, we simulate the performance and benchmark these predictions with experimental results when running the code on the superconducting quantum device. The results indicate that for small codes, the quasi-linear layout of the superconducting device is advantageous. Yet, for codes involving multi-qubit controlled operations, the central-spin connectivity of the color centers enables lower error rates.

DOI
10.1088/2058-9565/aca21f

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Abstract We evaluate the performance of small error-correcting codes, which we tailor to hardware platforms of very different connectivity and coherence: on a superconducting processor based on transmon qubits and a spintronic quantum register consisting of a nitrogen-vacancy center in diamond. Taking the hardware-specific errors and connectivity into account, we investigate the dependence of the resulting logical error rate on the platform features such as the native gates, native connectivity, gate times, and coherence times. Using a standard error model parameterized for the given hardware, we simulate the performance and benchmark these predictions with experimental results when running the code on the superconducting quantum device. The results indicate that for small codes, the quasi-linear layout of the superconducting device is advantageous. Yet, for codes involving multi-qubit controlled operations, the central-spin connectivity of the color centers enables lower error rates.
Color centers in diamond provide a possible hardware for quantum computation, where the most basic quantum information processing unit are nitrogen-vacancy (NV) centers, each in contact with adjacent carbon nuclear spins. With specifically tailored dynamical decoupling sequences, it is possible to execute selective, high-fidelity two-body gates between the electron spin of the NV center and a targeted nuclear spin. In this work, we present a method to determine the optimal execution time that balances the trade-off between fidelity and execution speed for gates generated by adaptive XY sequences. With these optimized gates, we use the nuclear spin environment as a code space for quantum error correction within a color center register.
Quantum error correction [1–4] is essential for bridging the gap between the error rates of physical devices and the extremely low error rates required for quantum algorithms. Recent error-correction demonstrations on superconducting processors [5–8] have focused primarily on the surface code [9], which offers a high error threshold but poses limitations for logical operations. The color code [10] enables more efficient logic, but it requires more complex stabilizer measurements and decoding. Measuring these stabilizers in planar architectures like superconducting qubits is challenging, and realizations of color codes [11–19] have not addressed performance scaling with code size on any platform. Here, we present a comprehensive demonstration of the color code on a superconducting processor [8]. Scaling the code distance from three to five suppresses logical errors by a factor of Λ 3/5 = 1.56(4). Simulations indicate this performance is below the threshold of the color code, and the color code may become more efficient than the surface code following modest device improvements. We test transversal Clifford gates with logical randomized benchmarking [20] and inject magic states [21], a key resource for universal computation, achieving fidelities exceeding 99 % with post-selection. Finally, we teleport logical states between color codes using lattice surgery [22]. This work establishes the color code as a compelling research direction to realize fault-tolerant quantum computation on superconducting processors in the near future.
Experimental realization of stabilizer-based quantum error correction (QEC) codes that would yield superior logical qubit performance is one of the formidable task for state-of-the-art quantum processors. A major obstacle toward realizing this goal is the large footprint of QEC codes, even those with a small distance. We propose a circuit based on the minimal distance-3 QEC code, which requires only five data qubits and five ancilla qubits, connected in a ring with iswap gates implemented between neighboring qubits. Using a density-matrix simulation, we show that, thanks to its smaller footprint, the proposed code has a lower logical error rate than surface-17 for similar physical error rates. We also estimate the performance of a neural-network-based error decoder, which can be trained to accommodate the error statistics of a specific quantum processor by training on experimental data.
Readout errors are one of the dominant sources of noise in current quantum processors, limiting both expectation-value estimation and sampling-based applications. Since they affect only the classical measurement outcomes, they can be addressed using classical coding techniques: immediately before measurement, each data qubit is redundantly encoded with ancilla qubits, and the resulting bit string is decoded either by post-selection or by majority voting. Unlike conventional readout error mitigation, which corrects only aggregate quantities such as expectation values, this approach operates on individual measurement shots and can therefore produce approximately corrected samples. We present a systematic cross-platform and cross-generation experimental evaluation of repetition-code readout error detection and correction. We benchmark the same protocol on IBM Heron r1-r3 superconducting processors and Quantinuum H1 and H2 trapped-ion processors while independently varying the code distance, hardware generation, and encoding layout. We find that both error detection and correction improve readout fidelity on every device and generation tested, even as the unencoded baseline improves substantially across successive hardware releases. At the same time, the value of additional redundancy depends strongly on the underlying hardware. On superconducting processors, the extra gate errors introduced by the encoding rapidly offset its benefits, whereas on trapped-ion processors the much lower gate error rates allow larger code distances to remain advantageous.
Error correcting codes use multi-qubit measurements to realize fault-tolerant quantum logic steps. In fact, the resources needed to scale-up fault-tolerant quantum computing hardware are largely set by this task. Tailoring next-generation processors for joint measurements, therefore, could result in improvements to speed, accuracy, or cost -- accelerating the development large-scale quantum computers. Here, we motivate such explorations by analyzing an unconventional surface code based on multi-body interactions between superconducting transmon qubits. Our central consideration, Hardware Optimized Parity (HOP) gates, achieves stabilizer-type measurements through simultaneous multi-qubit conditional phase accumulation. Despite the multi-body effects that underpin this approach, our estimates of logical faults suggest that this design can be at least as robust to realistic noise as conventional designs. We show a higher threshold of 1.25×10−31.25 \times 10^{-3}1.25×10−3 compared to the standard code's 0.79×10−30.79 \times 10^{-3}0.79×10−3. However, in the HOP code the logical error rate decreases more slowly with decreasing physical error rate. Our results point to a fruitful path forward towards extending gate-model platforms for error correction at the dawn of its empirical development.
Quantum error correction can suppress logical errors exponentially with code distance when physical noise is below threshold. Realizing this on hardware requires tight coordination among quantum gates, mid-circuit measurements, and qubit coherence. Device variation, noise asymmetry, and correlations across space and time complicate the translation of these capabilities into logical error suppression. Here, we study rotated surface-code memory on an IBM Nighthawk r2 processor. Performance varies across tested processor placements, which we attribute to differences in qubit quality. We optimize the code by combining short readout, fused measurement and reset, and an XX echo on data qubits during ancilla readout. Compared with standard readout without reset or echo, the optimized syndrome extraction circuit reduces the median per-round logical error rate by factors of 3.8 in the X basis and 1.4 in the Z basis. In memory experiments of up to 150 rounds, the distance advantage weakens, alongside long-lived correlations that may reflect a persistent error component. Under our optimization recipe, increasing the protected distance from 3 to 6 while holding the other distance fixed reduces the per-round logical error rate from 0.53% to 0.24% in Z memory and from 0.52% to 0.22% in X memory. The corresponding error-suppression factors under maximum-likelihood decoding are 1.68 and 1.85. These results connect circuit compilation and optimization to surface-code memory performance and limitations, and motivate QPU and QEC circuit codesign for fault-tolerant quantum computing primitives on current cloud hardware.