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arXiv:2107.06491 · Physical Review A

Simulation of the five-qubit quantum error correction code on superconducting qubits

Ilya A. Simakov, Ilya S. Besedin, Alexey Vladimirovich Ustinov

Published Mar 3, 2022• 7 citations
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Abstract

Experimental realization of stabilizer-based quantum error correction (QEC) codes that would yield superior logical qubit performance is one of the formidable task for state-of-the-art quantum processors. A major obstacle toward realizing this goal is the large footprint of QEC codes, even those with a small distance. We propose a circuit based on the minimal distance-3 QEC code, which requires only five data qubits and five ancilla qubits, connected in a ring with iswap gates implemented between neighboring qubits. Using a density-matrix simulation, we show that, thanks to its smaller footprint, the proposed code has a lower logical error rate than surface-17 for similar physical error rates. We also estimate the performance of a neural-network-based error decoder, which can be trained to accommodate the error statistics of a specific quantum processor by training on experimental data.

DOI
10.1103/physreva.105.032409

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Experimental realization of stabilizer-based quantum error correction (QEC) codes that would yield superior logical qubit performance is one of the formidable task for state-of-the-art quantum processors. A major obstacle toward realizing this goal is the large footprint of QEC codes, even those with a small distance. We propose a circuit based on the minimal distance-3 QEC code, which requires only five data qubits and five ancilla qubits, connected in a ring with iswap gates implemented between neighboring qubits. Using a density-matrix simulation, we show that, thanks to its smaller footprint, the proposed code has a lower logical error rate than surface-17 for similar physical error rates. We also estimate the performance of a neural-network-based error decoder, which can be trained to accommodate the error statistics of a specific quantum processor by training on experimental data.
Quantum Error Correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardware implementation has not been presented yet. This work presents a space exploration of fully-connected feed-forward NN decoders for small distance surface codes. The goal is to optimize the neural network for high decoding performance, while keeping a minimalistic hardware implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We demonstrate that hardware based NN-decoders can achieve high decoding performance comparable to other state-of-the-art decoding algorithms whilst being well below the tight delay requirements (440 ns) of current solid-state qubit technologies for both ASIC designs (<30 ns) and FPGA implementations (<90 ns). These results indicate that NN-decoders are viable candidates for further exploration of an integrated hardware implementation in future large-scale quantum computers.
Quantum error correction is an important ingredient for scalable quantum computing. Stabilizer codes are one of the most promising and straightforward ways to correct quantum errors, are convenient for logical operations, and improve performance with increasing the number of qubits involved. Here, we propose a resource-efficient scaling of a five-qubit perfect code with increasing-weight cyclic stabilizers for small distances on the ring architecture, which takes into account the topological features of the superconducting platform. We show an approach to construct the quantum circuit of a correction code with ancillas entangled with non-neighboring data qubits. Furthermore, we introduce a neural network-based decoding algorithm supported by an improved lookup table decoder and provide a numerical simulation of the proposed code, which demonstrates the exponential suppression of the logical error rate.
Current quantum processors are fragile, noisy and fairly limited in both quantity and quality with tens of qubits and physical error rates of around 10^-3. To realize practical quantum applications, however, error rates need to be below 10^-15 across millions of qubits. To bridge this gap and fully harness the potential of quantum computers, quantum error correction (QEC) is essential. QEC codes are designed to protect quantum information by redundantly encoding it onto multiple physical qubits. This encoding allows for the detection and correction of local errors affecting individual qubits, e.g., through stabilizer measurements. Importantly, if the physical error rates are below a specific threshold, QEC codes can exponentially suppress logical error rates by increasing the number of physical qubits involved. This is essential for achieving fault-tolerant computations, which are key to unlocking the full potential of quantum computers. The work presented in this thesis focuses on the implementation and optimization of small-scale QEC experiments using the surface code and flux-tunable superconducting qubits (Transmons). It addresses several key challenges: enhancing two-qubit gate fidelity in Surface-4 (Chapter 2), implementing an error-detection code with Surface-7 (Chapter 3), automating the calibration and benchmarking of the building blocks in Surface-17 (Chapter 4), reducing leakage into higher excited states with leakage reduction units (Chapter 5), assessing and enhancing the performance of logical qubits (Chapters 7 and 8).
Quantum error correction is an essential ingredient for universal quantum computing. Despite tremendous experimental efforts in the study of quantum error correction, to date, there has been no demonstration in the realisation of universal quantum error correction code (QECC), with the subsequent verification of all key features including the identification of an arbitrary physical error, the capability for transversal manipulation of the logical state, and state decoding. To address this notoriously difficult challenge, we push the limits of the depth of superconducting quantum circuits and experimentally realise the universal five-qubit QECC, the so-called smallest perfect code that permits corrections of generic single-qubit errors. In the experiment, having optimised the encoding circuit, we employ an array of superconducting qubits to realise the five-qubit QECC for several typical logical states including the magic state, an indispensable resource for realising non-Clifford gates. The encoded states are prepared with an average fidelity of 57.1(3)%57.1(3)\%57.1(3)% while with a high fidelity of 98.6(1)%98.6(1)\%98.6(1)% in the code space. Then, the arbitrary single-qubit errors introduced manually are identified by measuring the stabilizers. We further implement logical Pauli operations with a fidelity of 97.2(2)%97.2(2)\%97.2(2)% within the code space. Finally, we realise the decoding circuit and recover the input state with a process fidelity of 57.4(7)%57.4(7)\%57.4(7)%. After decoding, by identifying errors via the measurement of the four ancillae and then mathematically recovering the qubit state, we verify the power of error correction of this code. Thus, by demonstrating each key aspect of error correction with the five-qubit code, our work establishes the viability of experimental quantum error correction with superconducting qubits and paves the route to fault-tolerant quantum computing.
Abstract Fault-tolerant quantum computing requires many qubits with long lifetimes and accurate quantum gate operations. However, external noise limits the computing time and hampers accurate quantum gate operations. Quantum error correction (QEC) codes may extend such limits, but imperfect gate operations during QEC cause errors, which could cancel out QEC. We used density matrix simulations to examine the performance of QEC codes with five qubits. In current quantum devices, less than ten qubits are needed to conduct sufficient gate operations within their lifetime so that it is feasible to implement QEC codes. We analyzed the maximum tolerable error rate and error correction effect of individual QEC codes according to the qubit arrangement and gate accuracy. Assuming a 0.1% gate error probability, a logical ∣ 1 〉 state encoded by a five-qubit QEC code is expected to have a 0.25 higher fidelity than its physical counterpart.
Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.