Noisy Intermediate-Scale Quantum (NISQ) algorithms, which run on noisy quantum computers should be carefully designed to boost the output state fidelity. While several compilation approaches have been proposed to minimize circuit errors, they often omit the detailed circuit structure information that does not affect the circuit depth or the gate count. In the presence of spatial variation in the error rate of the quantum gates, adjusting the circuit structure can play a major role in mitigating errors. In this paper, we exploit the freedom of gate reordering based on the commutation rules to show the impact of gate error propagation paths on the output state fidelity of the quantum circuit, propose advanced predictive techniques to project the success rate of the circuit, and develop a new compilation phase post-quantum circuit mapping to improve its reliability. Our proposed approaches have been validated using a variety of quantum circuits with different success metrics, which are executed on IBM quantum computers. Our results show that rescheduling quantum gates based on their error propagation paths can significantly improve the fidelity of the quantum circuit in the presence of variable gate error rates.
Noisy Intermediate-Scale Quantum (NISQ) algorithms, which run on noisy quantum computers should be carefully designed to boost the output state fidelity. While several compilation approaches have been proposed to minimize circuit errors, they often omit the detailed circuit structure information that does not affect the circuit depth or the gate count. In the presence of spatial variation in the error rate of the quantum gates, adjusting the circuit structure can play a major role in mitigating errors. In this paper, we exploit the freedom of gate reordering based on the commutation rules to show the impact of gate error propagation paths on the output state fidelity of the quantum circuit, propose advanced predictive techniques to project the success rate of the circuit, and develop a new compilation phase post-quantum circuit mapping to improve its reliability. Our proposed approaches have been validated using a variety of quantum circuits with different success metrics, which are executed on IBM quantum computers. Our results show that rescheduling quantum gates based on their error propagation paths can significantly improve the fidelity of the quantum circuit in the presence of variable gate error rates.
Noisy intermediate-scale quantum algorithms, which run on noisy quantum computers, should be carefully designed to boost the output state fidelity. While several compilation approaches have been proposed to minimize circuit errors, they often omit the detailed circuit structure information that does not affect the circuit depth or the gate count. In the presence of spatial variation in the error rate of the quantum gates, adjusting the circuit structure can play a major role in mitigating errors. In this article, we exploit the freedom of gate reordering based on the commutation rules to show the impact of gate error propagation paths on the output state fidelity of the quantum circuit, propose advanced predictive techniques to project the success rate of the circuit, and develop a new compilation phase postquantum circuit mapping to improve its reliability. Our proposed approaches have been validated using a variety of quantum circuits with different success metrics, which are executed on IBM quantum computers. Our results show that rescheduling quantum gates based on their error propagation paths can significantly improve the fidelity of the quantum circuit in the presence of variable gate error rates.
Quantum computing, leveraging the principles of superposition and entanglement, holds the potential to revolutionize computational problem-solving across a wide array of fields, from cryptography to complex system simulations. However, unlocking the full power of quantum computing requires the development of advanced quantum compilation techniques that can efficiently map high-level algorithms onto physical quantum hardware. This paper delves into state-of-the-art optimization strategies within quantum compilers, with a particular focus on methods such as Relaxed Peephole Optimization (RPO), gate reordering techniques for the Quantum Approximate Optimization Algorithm (QAOA), and reinforcement learning (RL)-driven frameworks. It also explores innovative approaches like distributed quantum compilation, parity quantum optimization, and the Paulihedral framework, all designed to minimize gate counts, reduce circuit depth, and optimize overall resource utilization. A key contribution of this work is the introduction of error mitigation techniques that enhance the fidelity and scalability of quantum circuits, particularly on noisy intermediate-scale quantum (NISQ) devices. Through comprehensive empirical evaluations across a variety of quantum algorithms, the paper demonstrates significant improvements in critical performance metrics such as circuit depth, gate count, and execution efficiency, providing a promising direction for optimizing quantum circuit design tailored to diverse quantum hardware platforms.
Noisy Intermediate-Scale Quantum (NISQ) devices are promising platforms for practical quantum computing, but their performance is significantly affected by limited qubit availability, gate errors, decoherence, circuit depth, and hardware-dependent noise. Conventional quantum circuits are generally designed and optimized before execution and may not respond effectively to changing hardware conditions during computation. This research proposes a Self-Adaptive Quantum Circuit framework that dynamically modifies quantum circuits according to the current computational resources and noise characteristics of NISQ devices. The proposed framework monitors parameters such as qubit fidelity, gate error rates, circuit depth, execution time, and resource availability, and automatically selects suitable circuit configurations to improve computational performance. Adaptive mechanisms can be employed to reduce unnecessary gates, optimize qubit utilization, and mitigate the impact of hardware noise while maintaining the required computational accuracy. The framework will be evaluated using simulation platforms and available NISQ quantum hardware, comparing adaptive circuits with conventional static circuits using metrics such as accuracy, fidelity, circuit depth, gate count, execution time, and error rate. The expected outcome is a resource-efficient and noise-aware quantum circuit optimization approach capable of improving the reliability and performance of quantum applications on near-term quantum hardware. The proposed research aims to contribute toward more practical, flexible, and hardware-aware quantum computing systems for NISQ-era applications. Keywords: NISQ Computing, Self-Adaptive Quantum Circuits, Quantum Circuit Optimization, Quantum Error Mitigation, Quantum Noise, Quantum Computing.
Quantum circuit compilers play an important role in mitigating errors of quantum circuits executed on Noisy Intermediate-Scale Quantum (NISQ) computers. The compiler maps the quantum algorithm into a physical quantum circuit that satisfies the physical constraints of NISQ architecture. However, the reliability of NISQ computers is still very challenging. In this work, we design a new class of quantum test circuits using flag qubits based on error propagation. Furthermore, we automate the test point insertion. Our approach can detect errors at different points in the circuit to assess its output reliability. The goal is to select a qubit allocation that improves the quantum circuit output fidelity. We show the effectiveness of our approach using an IBM quantum computer and a noisy simulator.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.