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arXiv:2109.00560 · Superconductor Science and Technology

Synchronous chip-to-chip communication with a multi-chip resonator clock distribution network *

Jonathan Egan, Max Nielsen, Joshua Strong, Vladimir V. Talanov, Ed Rudman, Brainton Song, Quentin Herr, Anna Herr

Published Aug 31, 2022• 11 citations
arXivHTMLPDF

Abstract

Abstract Superconducting digital circuits are a promising approach to build integrated systems with high energy-efficiency and computational density of the packaged chips. In such systems, performance of the data link between chips mounted on a multi-chip-module (MCM) is a critical driver of performance. In this work we report a synchronous data link using reciprocal quantum logic enabled by resonant clock distribution on-chip and on the MCM carrier. The simple physical link has only four Josephson junctions and 3 fJ/bit dissipation, including a 300 W/W cooling overhead. The driver produces a signal with 35 GHz analog bandwidth and connects to a single-ended receiver via 20 Ω Nb passive transmission line. To validate this link, we have designed, fabricated, and tested two 32 × 32 mm2 MCMs with eight 5 × 5 mm2 chips connected serially and powered by a traveling-wave clock, and with four 10 × 10 mm2 chips powered with a 2 GHz resonant clock. The traveling-wave clock MCM validates performance of the data link components and achieves a 5.4 dB AC bias margin with no degradation relative to individual chip tests. The resonator MCM validates synchronization between chips, with a measured AC bias margin up to 4.8 dB between two chips. The resonator MCM is capable of powering circuits of 4 million Josephson junctions across the four chips with a projected 10 Gbps serial data rate.

DOI
10.1088/1361-6668/ac8e38

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Abstract Superconducting digital circuits are a promising approach to build integrated systems with high energy-efficiency and computational density of the packaged chips. In such systems, performance of the data link between chips mounted on a multi-chip-module (MCM) is a critical driver of performance. In this work we report a synchronous data link using reciprocal quantum logic enabled by resonant clock distribution on-chip and on the MCM carrier. The simple physical link has only four Josephson junctions and 3 fJ/bit dissipation, including a 300 W/W cooling overhead. The driver produces a signal with 35 GHz analog bandwidth and connects to a single-ended receiver via 20 Ω Nb passive transmission line. To validate this link, we have designed, fabricated, and tested two 32 × 32 mm2 MCMs with eight 5 × 5 mm2 chips connected serially and powered by a traveling-wave clock, and with four 10 × 10 mm2 chips powered with a 2 GHz resonant clock. The traveling-wave clock MCM validates performance of the data link components and achieves a 5.4 dB AC bias margin with no degradation relative to individual chip tests. The resonator MCM validates synchronization between chips, with a measured AC bias margin up to 4.8 dB between two chips. The resonator MCM is capable of powering circuits of 4 million Josephson junctions across the four chips with a projected 10 Gbps serial data rate.
Abstract Interconnect properties position superconducting digital circuits to build large, high performance, power efficient digital systems. We report a board-to-board communication data link, which is a critical technological component that has not yet been addressed. Synchronous communication on chip and between chips mounted on a common board is enabled by the superconducting resonant clock/power network for Reciprocal Quantum Logic circuits. The data link is extended to board-to-board communication using isochronous communication, where there is a common frequency between boards but the relative phase is unknown. Our link uses over-sampling and configurable delay at the receiver to synchronize to the local clock phase. A single-bit isochronous data link has been demonstrated on-chip through a transmission line, and on a multi-chip module through a superconducting tape between driver and receiver with variable phase offset. Measured results demonstrated correct functionality with a clock margin of 3 dB at 3.6 GHz, and with 5 fJ bit−1 at 4.2 K.
We present test results for parallel data communication ERSFQ circuits with clock recovery. We experimentally study on-chip and chip-to-chip parallel data communication circuits with 4-, 8- and 16-bit word lengths. The largest circuit is a 16-bit chip-to-chip communication test circuit embedded into a testbed with clock distributed over a combination of active and passive transmission lines with transmitter/receiver pairs, and is comprised of 3464 Josephson junctions in total. All ERSFQ circuits are fabricated using MITLL 10-kA/cm2SFQ5ee process. For the chip-to-chip communication experiment, a multi-chip module (MCM) is assembled using Hypres' MCM flip-chip bonding process which connected the MIT-LL-made flip-chip to the Hypres-made MCM carrier using 220 signal bumps with 50 um pitch. We experimentally confirmed correct functionality of 4-, 8- and 16-bit circuits and measured their current bias margins. For the 16- bit chip-to-chip communication circuit mounted to a MCM, we measured ±12% dc bias margins similar to the margins measured for the on-chip version of the same circuit. The MCM circuit is also evaluated at high clock speed generated by an external source, while the data words are changed at low speed. The correct functionality is observed without significant reduction in the bias margins using average-voltage test approach.
This paper presents the results of theoretical optimization of the multi-chip-module (MCM) contact and driver circuitries for gigabit chip-to-chip communication. Optimization has been done using 3D electromagnetic (EM) simulations of MCM contacts and time domain simulations of drivers and receivers. A single optimized MCM contact has a signal reflection of less than −20 dB for more than 400 GHz bandwidth. The MCM data link with the optimized SFQ driver, receiver and two MCM contacts has operational margins on the global bias current of ± 30% at 30 Gbit s −1 speedand can operate above 100 Gbit s −1 speed. Wide bandwidth transmission requires the realization of an advanced flip–chip process with a small dimension of the MCM contact (less than 30 µm diameter of the contact pad) and small height of the flip–chip contact bumps of the order of 2 µm. Current processes with about 7 µm height of the bumps require the application of a double-flux-quantum (DFQ) driver. The data link with the DFQ driver was also simulated. It has operational margins on the global bias current of ± 30% at 30 Gbit s −1 ; however, the maximum speed of operation is 61 Gbit s −1 . Several test structures have been designed for measurements of signal reflection, bit error rate and operational margins of the data link.
Superconductor digital devices using single-flux-quantum (SFQ) data encoding offer higher speed at lower power than any other integrated circuit technology. For this very reason, interconnect is challenging. We report SFQ data transfer between chips flip chip mounted on a passive microstrip carrier. The flip-chip structure achieves bandwidths greater than 250 GHz. Unlike previous designs, our signal lines are terminated at both ends; this is accomplished using a driver that produces a double-flux-quantum signal. We measured the circuit for pseudorandom data in the range of 10–60 Gb/s. Bit error rates are measured down to 1E−10 and extrapolate to negligible values. The signal power on the microstrip is only 30 nW at 60 Gb ps.
We recently reported communication up to 60 Gb/s between digital superconductor chips mounted on a passive carrier, using a novel driver circuit that produces a double-flux-quantum pulse. Here, we answer various practical questions pertaining to chip-to-chip and on-chip communication in greater detail. On-chip, the traditional single-flux-quantum driver is adequate, although margins and bit error rate degrade significantly at the microstrip resonance frequency. Chip-to-chip, using the double-flux-quantum driver, shows little frequency dependence, in spite of 13% reduction of signal current in the chip-to-chip transitions. Appropriate microstrip impedance is in the range 4-8 /spl Omega/ for a 4 kA/cm/sup 2/ Josephson junction IC process. Data includes bit errors rates for pseudo-random data in the range 3-27 Gb/s.
Superconducting single flux quantum (SFQ) circuits can process information at extremely high speeds, in the range of hundreds of GHz. SFQ circuits are based on Josephson junction cells for switching logic and ballistic transmission for transferring SFQ pulses. Multi-chip modules (MCMs) are often used to implement larger complex designs, which cannot be fit onto a single chip. We have optimized the design of wideband interconnects for transferring signals and SFQ pulses between chips in flip-chip MCMs and evaluated the importance of several design parameters such as the geometry of bump pads on chips, length of passive microstrip lines (MSLs) and number of corners in MSLs as well as flux trapping and fabrication effects on the operating margins of the MCMs. Several test circuits have been designed to evaluate the above mentioned features and fabricated in the framework of a 4.5 kA cm −2 HYPRES process. The MCM bumps for electrical connections have been deposited using a wafer-level electroplating process. We have found that, at the optimized configuration, the maximum operating frequency of the MCM test circuit, a ring oscillator with chip-to-chip connections, approaches 100 GHz and is not noticeably affected by the presence of MCM interconnects, decreasing by only about 3% with respect to the same circuit with no inter-chip connections.