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arXiv:2106.10488 · Symposium on VLSI Circuits

Superconducting quantum computer: a hint for building architectures

Yutaka Tabuchi, Shuhei Tamate, Shinichi Yorozu

Published Jun 13, 2021• 0 citations
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Abstract

We discuss the scalability of superconducting quantum computers, especially in a wiring problem. The number of wiring inside a cryostat is almost proportional to the number of qubits in the current wiring architecture. We introduce "The three-Y’s": regularity, modularity, and hierarchy to an architecture design of superconducting quantum computers. The key to the wiring elimination is found in the quantum error correction codes having thresholds and spatial translational symmetry, i.e., the surface code. We show a superconducting-digital-logic-based architecture and introduce a stacked heterogeneous structure of the quantum module.

DOI
10.23919/vlsicircuits52068.2021.9492416

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We discuss the scalability of superconducting quantum computers, especially in a wiring problem. The number of wiring inside a cryostat is almost proportional to the number of qubits in the current wiring architecture. We introduce "The three-Y’s": regularity, modularity, and hierarchy to an architecture design of superconducting quantum computers. The key to the wiring elimination is found in the quantum error correction codes having thresholds and spatial translational symmetry, i.e., the surface code. We show a superconducting-digital-logic-based architecture and introduce a stacked heterogeneous structure of the quantum module.
Quantum computing architectures with ten or more quantum bits (qubits) have been implemented using trapped ions and superconducting devices. The next milestone in the quest for a quantum computer is the realization of quantum error correction codes. Such codes will require a large number of qubits that must be controlled and measured by means of classical electronics. This scaling up leads to a number of problems and sources of error that must be accounted for in order to have an operational system. \n \nOne architectural aspect requiring immediate attention is the realization of a suitable interconnect between the quantum and classical hardware. Our proposed solution to this wiring problem is the quantum socket, a three-dimensional wiring method for qubits with superior performance as compared to two-dimensional methods based on wire bonding. The quantum socket also provides a means to counteract another scaling problem, the coupling of qubits to unwanted cavity modes resulting in coherent leakage error. By following our proposed wiring methodologies, half-wave fencing or antinode pinning, we show how the error due to leakage can be mitigated to orders of magnitude below current state-of-the-art error probabilities.
This work presents a conceptual architecture and technological roadmap for a scalable superconducting quantum computing platform based on modular design principles. Rather than introducing a new qubit technology, the proposal focuses on addressing critical engineering bottlenecks that currently limit the large-scale deployment of quantum processors, including wiring complexity, electromagnetic crosstalk, fabrication yield, and latency in error-correction feedback loops.The proposed framework introduces a modular hybrid architecture (“Quantum Mesh”), where medium-scale quantum chiplets containing 25–50 superconducting transmon qubits are interconnected through advanced 3D packaging and cryogenic infrastructure. This approach aims to improve manufacturing yield, reduce wiring density, and enable rack-level integration of quantum processing units while maintaining high gate fidelities and manageable thermal loads.A second central element of the proposal is the integration of a high-fidelity digital twin environment capable of simulating qubit dynamics, noise sources, control latency, and thermal constraints at nanosecond resolution. This predictive framework is intended to support hardware iteration cycles prior to fabrication, potentially accelerating design optimization and system validation.The document outlines a three-year development pathway targeting 100–200 physical qubits and several logical qubits using surface code error correction, followed by a longer-term scaling strategy toward quantum fabrics exceeding one thousand qubits. By combining modular quantum chiplets, partial cryogenic electronics, and predictive digital twin modeling, the proposed architecture explores a plausible industrial pathway toward large-scale quantum computing systems.
Abstract Among the major hardware platforms for large-scale quantum computing, one of the leading candidates is superconducting quantum circuits. Current proposed architectures for quantum error-correction with the promising surface code require a two-dimensional layout of superconducting qubits with nearest-neighbor interactions. A major hurdle for the scalability in such an architecture using superconducting systems is the so-called wiring problem, where qubits internal to a chipset become difficult to access by the external control/readout lines. In contrast to the existing approaches which address the problem through intricate three-dimensional wiring and packaging technology, leading to a significant engineering challenge, here we address this problem by presenting a modified microarchitecture in which all the wiring can be realized through a newly introduced pseudo two-dimensional resonator network which provides the inter-qubit connections via airbridges. Our proposal is completely compatible with current standard planar circuit technology. We carried out experiments to examine the feasibility of the new airbridge component. The measured quality factor of the airbridged resonator is below the simulated surface-code threshold required for a coupling resonator, and it should not limit simulated gate fidelity. The measured crosstalk between crossed resonators is at most −49 dB in resonance. Further spatial and frequency separation between the resonators should result in relatively limited crosstalk between them, which would not increase as the size of the chipset increases. This architecture and the preliminary tests indicate the possibility that a large-scale, fully error-corrected quantum computer could be constructed by monolithic integration technologies without additional overhead or special packaging know-how.
Scaling superconducting quantum computers to the fault-tolerant regime calls for a commensurate scaling of the classical control and readout stack. Today's systems largely rely on room-temperature, rack-based instrumentation connected to dilution-refrigerator cryostats through many coaxial cables. Looking ahead, superconducting fault-tolerant quantum computers (FTQCs) will likely adopt a heterogeneous quantum-classical architecture that places selected electronics at cryogenic stages -- for example, cryo-CMOS at 4~K and superconducting digital logic at 4~K and/or mK stages -- to curb wiring and thermal-load overheads. This review distills key requirements, surveys representative room-temperature and cryogenic approaches, and provides a transparent first-order accounting framework for cryoelectronics. Using an RSA-2048-scale benchmark as a concrete reference point, we illustrate how scaling targets motivate constraints on multiplexing and stage-wise cryogenic power, and discuss implications for functional partitioning across room-temperature electronics, cryo-CMOS, and superconducting logic.
In the span of four decades, quantum computation has evolved from an intellectual curiosity to a potentially realizable technology. Today, small-scale demonstrations have become possible for quantum algorithmic primitives on hundreds of physical qubits. Nevertheless, there are significant outstanding challenges in quantum hardware, fabrication, software architecture, and algorithms on the path towards a full-stack scalable quantum computing technology. Here, we provide a comprehensive review of these scaling challenges. We show how to facilitate scaling by adopting existing semiconductor technology to build much higher-quality qubits, employing systems engineering approaches, and performing distributed heterogeneous quantum-classical computing. We provide a detailed resource and sensitivity analysis for quantum applications on surface-code error-corrected quantum computers given current, target, and desired hardware specifications based on superconducting qubits, accounting for a realistic distribution of errors. We provide comprehensive resource estimates for several utility-scale applications including quantum chemistry calculations, catalyst design, NMR spectroscopy, and Fermi-Hubbard simulation. We show that orders of magnitude enhancement in performance could be obtained by a combination of hardware improvements and tight quantum-HPC integration. Furthermore, we introduce high-performance architectures for quantum-probabilistic computing with custom-designed accelerators to tackle today's industry-scale classical optimization, machine learning, and quantum simulation tasks in a cost-effective manner.