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arXiv:2104.03335 · IEEE Transactions on Quantum Engineering

Single-Qubit Fidelity Assessment of Quantum Annealing Hardware

Jon Nelson, Marc Vuffray, Andrey Y. Lokhov, Carleton Coffrin

Published Jan 1, 2021• 19 citations
arXivHTMLPDF

Abstract

As a wide variety of quantum computing platforms become available, methods for assessing and comparing the performance of these devices are of increasing interest and importance. Inspired by the success of single-qubit error rate computations for tracking the progress of gate-based quantum computers, this work proposes a quantum annealing single-qubit assessment (QASA) protocol for quantifying the performance of individual qubits in quantum annealing computers. The proposed protocol scales to large quantum annealers with thousands of qubits and provides unique insights into the distribution of qubit properties within a particular hardware device. The efficacy of the QASA protocol is demonstrated by analyzing the properties of a D-Wave 2000Q system, revealing unanticipated correlations in the qubit performance of that device. A study repeating the QASA protocol at different annealing times highlights how the method can be utilized to understand the impact of annealing parameters on qubit performance. Overall, the proposed QASA protocol provides a useful tool for assessing the performance of current and emerging quantum annealing devices.

DOI
10.1109/tqe.2021.3092710

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As a wide variety of quantum computing platforms become available, methods for assessing and comparing the performance of these devices are of increasing interest and importance. Inspired by the success of single-qubit error rate computations for tracking the progress of gate-based quantum computers, this work proposes a quantum annealing single-qubit assessment (QASA) protocol for quantifying the performance of individual qubits in quantum annealing computers. The proposed protocol scales to large quantum annealers with thousands of qubits and provides unique insights into the distribution of qubit properties within a particular hardware device. The efficacy of the QASA protocol is demonstrated by analyzing the properties of a D-Wave 2000Q system, revealing unanticipated correlations in the qubit performance of that device. A study repeating the QASA protocol at different annealing times highlights how the method can be utilized to understand the impact of annealing parameters on qubit performance. Overall, the proposed QASA protocol provides a useful tool for assessing the performance of current and emerging quantum annealing devices.
As a variety of quantum computing models and platforms become available, methods for assessing and comparing the performance of these devices are of increasing interest and importance. Despite being built of the same fundamental computational unit, radically different approaches have emerged for characterizing the performance of qubits in gate-based and quantum annealing computers, limiting and complicating consistent cross-platform comparisons. To fill this gap, this work proposes a single-qubit protocol (Q-RBPN) for measuring some basic performance characteristics of individual qubits in both models of quantum computation. The proposed protocol scales to large quantum computers with thousands of qubits and provides insights into the distribution of qubit properties within a particular hardware device and across families of devices. The efficacy of the Q-RBPN protocol is demonstrated through the analysis of more than 300 gate-based qubits spanning eighteen machines and 2000 annealing-based qubits from one machine, revealing some unexpected differences in qubit performance. Overall, the proposed Q-RBPN protocol provides a new platform-agnostic tool for assessing the performance of a wide range of emerging quantum computing devices.
Quantum annealing is an emerging metaheuristic used for solving combinatorial optimisation problems. However, hardware based physical quantum annealers are primarily limited to a single vendor. As an alternative, we can discretise the quantum annealing process (discretised quantum annealing or DiQA) and use it on gate-model quantum computers. In this work, we first benchmark DiQA against simulated annealing for a similar number of steps. We then propose and evaluate a hybrid quantum classical heuristic: Quantum Accelerated Simulated Annealing (QASA), where the traditional classical annealing procedure can be sped up with the use of (relatively) low depth DiQA circuits. This is done by (i) running a partial annealing scheme with a fraction of the depth of the complete circuit (ii) sampling the results from the circuit and fitting a Gibbs distribution on it and (iii) Using the inverse temperature of the Gibbs distribution and the best sample to initialise simulated annealing (SA). Our simulation results show QASA performing comparably to SA but for a reduced amount of steps. With the promising results of our work, we hope to generate interest for potential future work in the area of fixed-parameter quantum optimisation.
Quantum annealing is an emerging metaheuristic used for solving combinatorial optimisation problems. However, hardware based physical quantum annealers are primarily limited to a single vendor. As an alternative, we can discretise the quantum annealing process (discretised quantum annealing or DiQA) and use it on gate-model quantum computers. In this work, we first benchmark DiQA against simulated annealing for a similar number of steps. We then propose and evaluate a hybrid quantumclassical heuristic: Quantum Accelerated Simulated Annealing (QASA), where the traditional classical annealing procedure can be sped up with the use of (relatively) low depth DiQA circuits. This is done by (i) running a partial annealing scheme with a fraction of the depth of the complete circuit (ii) sampling the results from the circuit and fitting a Gibbs distribution on it and (iii) Using the inverse temperature of the Gibbs distribution and the best sample to initialise simulated annealing (SA). Our simulation results show QASA performing comparably to SA but for a reduced amount of steps.With the promising results of our work, we hope to generate interest for potential future work in the area of fixed-parameter quantum optimisation.
Abstract Quantum computing is no longer a nascent field. Programmable quantum annealing (QA) devices with more than 1000 qubits are commercially available. How does one know that a putative QA device is indeed quantum? How should one go about benchmarking its performance and compare it to classical algorithms? How can its performance be improved by error correction? In this contribution to the focus collection on ‘What would you do with 1000 qubits?’, we review the work we and others have done in this area, since the first D-Wave quantum annealer with 108 qubits was made available to us. Some of the lessons we have learned will be useful when other quantum computing platforms reach a similar scale, and practitioners will attempt to demonstrate quantum speedup.
With the continued scaling of quantum processors, holistic benchmarks are essential for extensively evaluating device performance. Layer fidelity is a benchmark well-suited to assessing processor performance at scale. Key advantages of this benchmark include its natural alignment with randomized benchmarking (RB) procedures, crosstalk awareness, fast measurements over large numbers of qubits, high signal-to-noise ratio, and fine-grained information [1]. In this work, we extend the analysis of the original layer fidelity manuscript to optimize parameters of the benchmark and extract deeper insights of its application. We present a robust protocol for identifying optimal qubit chains of arbitrary lengthNNN, demonstrating that our method yields error per layered gate (EPLG) values40%−70%40 \% - 70 \%40%−70%lower than randomly selected chains forN=100N=100N=100qubits. We further establish layer fidelity as an effective performance monitoring tool, capturing both edge-localized and device-wide degradation by tracking optimal chains of length 50 and 100, and fixed chains of length 100. Additionally, we refine error analysis by proposing parameter bounds on the number of randomizations and Clifford lengths used in direct RB fits, minimizing fit uncertainties. Finally, we use layer fidelity to analyze the impact of varying gate durations on layered two-qubit (2Q) errors, showing that prolonged gate times leading to idling times significantly increase these quantities. These findings extend the applicability of the layer fidelity benchmark and provide practical guidelines for optimizing quantum processor evaluations.
Over the past decade, the usefulness of quantum annealing hardware for combinatorial optimization has been the subject of much debate. Thus far, experimental benchmarking studies have indicated that quantum annealing hardware does not provide an irrefutable performance gain over state-of-the-art optimization methods. However, as this hardware continues to evolve, each new iteration brings improved performance and warrants further benchmarking. To that end, this work conducts an optimization performance assessment of D-Wave Systems' most recent Advantage Performance Update computer, which can natively solve sparse unconstrained quadratic optimization problems with over 5,000 binary decision variables and 40,000 quadratic terms. We demonstrate that classes of contrived problems exist where this quantum annealer can provide run time benefits over a collection of established classical solution methods that represent the current state-of-the-art for benchmarking quantum annealing hardware. Although this work does not present strong evidence of an irrefutable performance benefit for this emerging optimization technology, it does exhibit encouraging progress, signaling the potential impacts on practical optimization tasks in the future.