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arXiv:1912.06461 · Technical digest - International Electron Devices Meeting/Technical digest

A sparse spin qubit array with integrated control electronics

Jelmer M. Boter, J. P. Dehollain, Jeroen P. G. van Dijk, Toivo Hensgens, R. Versluis, J. S. Clarke, Menno Veldhorst, Fabio Sebastiano, Lieven M. K. Vandersypen

Published Dec 1, 2019• 14 citations
arXivHTMLPDF

Abstract

Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.

DOI
10.1109/iedm19573.2019.8993570

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Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.
One of the main bottlenecks in the pursuit of a large-scale--chip-based quantum computer is the large number of control signals needed to operate qubit systems. As system sizes scale up, the number of terminals required to connect to off-chip control electronics quickly becomes unmanageable. Here, we discuss a quantum-dot spin-qubit architecture that integrates on-chip control electronics, allowing for a significant reduction in the number of signal connections at the chip boundary. By arranging the qubits in a two-dimensional array with about $12\phantom{\rule{0.2em}{0ex}}\ensuremath{\mu}\mathrm{m}$ pitch, we create space to implement locally integrated sample-and-hold circuits. This allows us to offset the inhomogeneities in the potential landscape across the array and to globally share the majority of the control signals for qubit operations. We make use of advanced circuit modeling software to go beyond conceptual drawings of the component layout, to assess the feasibility of the scheme through a concrete floor plan, including estimates of footprints for quantum and classical electronics, as well as routing of signal lines across the chip using different interconnect layers. We make use of local demultiplexing circuits to achieve an efficient signal-connection scaling, leading to a Rent's exponent as low as p=0.43p=0.43p=0.43. Furthermore, we use available data from state-of-the-art spin qubit and microelectronics technology development, as well as circuit models and simulations, to estimate the operation frequencies and power consumption of a million-qubit array. This work presents a complementary approach to previously proposed architectures, focusing on a feasible scheme to integrating quantum and classical hardware, and identifying remaining challenges for achieving full fault-tolerant quantum computation. It thereby significantly closes the gap towards a fully CMOS-compatible quantum computer implementation.
Scaling bottlenecks the making of digital quantum computers, posing challenges from both the quantum and the classical components. We present a classical architecture to cope with a comprehensive list of the latter challenges all at once , and implement it fully in an end-to-end system by integrating a multi-core RISC-V CPU with our in-house control electronics. Our architecture enables scalable, high-precision control of large quantum processors and accommodates evolving requirements of quantum hardware. A central feature is a microarchitecture executing quantum operations in parallel on arbitrary predefined qubit groups. Another key feature is a reconfigurable quantum instruction set that supports easy qubit re-grouping and instructions extensions. As a demonstration, we implement the widely-studied surface code quantum computing workflow, which is instructive for being demanding on both the controllers and the integrated classical computation. Our design, for the first time, reduces instruction issuing and transmission costs to constants, which do not scale with the number of qubits, without adding any overheads in decoding or dispatching. Our system uses a dedicated general-purpose CPU for both qubit control and classical computation, including syndrome decoding. Implementing recent theoretical proposals as decoding firmware that parallelizes general inner decoders, we can achieve unprecedented decoding capabilities of up to distances 47 and 67 with the currently available systems-on-chips for physical error rate p = 0.001 and p = 0.0001, respectively, all in just 1 μs.
Quantum computing holds the promise to solve problems that are currently intractable by classical computing platforms. Such computing framework relies on the properties of quantum bits (qubits) that operates at cryogenic temperatures well below 1K. Besides a quantum processor, an operational quantum computer needs a classical electronic controller reading out the electrical signals generated by the qubits and the providing electrical control to perform the required operations on the qubits. Since today’s quantum processors comprise a low number of qubits (<10), most controlling electronics can operate at room temperature and be connected by bulky interconnects to the cryogenic qubit chamber. However, when scaling up to the thousands of qubits required in a practical quantum algorithm, the classical electronics must be placed at cryogenic temperature to simplify the interconnects and allow a compact, reliable and scalable system. In this work, we propose the fully-integrated implementation in standard CMOS technology of the electronic read-out for spin qubits. Simulations show that the proposed current read-out circuit can achieve a 10MHz bandwidth that is 10X wider than current state-of-the-art read-outs while keeping comparable noise performance and operating at 4.2K. Such results are a promising indication that cryogenic CMOS circuits can provide the building blocks for the integration of the classical electronic controller for future scalable quantum computers.
Quantum processor architectures must enable scaling to large qubit numbers while providing two-dimensional qubit connectivity and exquisite operation fidelities. For microwave-controlled semiconductor spin qubits, dense arrays have made considerable progress, but are still limited in size by wiring fan-out and exhibit significant crosstalk between qubits. To overcome these limitations, we introduce the SpinBus architecture, which uses electron shuttling to connect qubits and features low operating frequencies and enhanced qubit coherence. Device simulations for all relevant operations in the Si/SiGe platform validate the feasibility with established semiconductor patterning technology and operation fidelities exceeding 99.9%. Control using room temperature instruments can plausibly support at least 144 qubits, but much larger numbers are conceivable with cryogenic control circuits. Building on the theoretical feasibility of high-fidelity spin-coherent electron shuttling as key enabling factor, the SpinBus architecture may be the basis for a spin-based quantum processor that meets the scalability requirements for practical quantum computing.
Future universal quantum computers solving problems of practical relevance are expected to require at least 10610^6106 qubits, which is a massive scale-up from the present numbers of less than 50 qubits operated together. Out of the different types of qubits, solid state qubits are considered to be viable candidates for this scale-up, but interfacing to and controlling such a large number of qubits is a complex challenge that has not been solved yet. One possibility to address this challenge is to use qubit control circuits located close to the qubits at cryogenic temperatures. In this work we evaluate the feasibility of this idea, taking as a reference the physical requirements of a two-electron spin qubit and the specifications of a standard 65 nm complementary metal-oxide-semiconductor (CMOS) process. Using principles and flows from electrical systems engineering we provide realistic estimates of the footprint and of the power consumption of a complete control-circuit architecture. Our results show that with further research it is possible to provide scalable electrical control in the vicinity of the qubit, with our concept.