Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

arXiv:1709.02402 · Quantum Science and Technology

High coherence plane breaking packaging for superconducting qubits

Nicholas T. Bronn, Vivekananda P Adiga, Salvatore B Olivadese, Xian Wu, Jerry M Chow, David P Pappas

Published Jan 9, 2018• 44 citations
arXivHTMLPDF

Abstract

We demonstrate a pogo pin package for a superconducting quantum processor specifically designed with a nontrivial layout topology (e.g., a center qubit that cannot be accessed from the sides of the chip). Two experiments on two nominally identical superconducting quantum processors in pogo packages, which use commercially available parts and require modest machining tolerances, are performed at low temperature (10 mK) in a dilution refrigerator and both found to behave comparably to processors in standard planar packages with wirebonds where control and readout signals come in from the edges. Single- and two-qubit gate errors are also characterized via randomized benchmarking, exhibiting similar error rates as in standard packages, opening the possibility of integrating pogo pin packaging with extensible qubit architectures.

DOI
10.1088/2058-9565/aaa645

Related papers

Mitigating leakage errors due to cavity modes in a superconducting quantum computer

Thomas McConkey, J. H. Béjanin, C. T. Earnest +4 more

Abstract A practical quantum computer requires quantum bit (qubit) operations with low error probabilities in extensible architectures. We study a packaging method that makes it possible to address hundreds of superconducting qubits by means of coaxial Pogo pins. A qubit chip is housed in a superconducting box, where both box and chip dimensions lead to unwanted modes that can interfere with qubit operations. We analyze these interference effects in the context of qubit coherent leakage and qubit decoherence induced by damped modes. We propose two methods, half-wave fencing and antinode pinning , to mitigate the resulting errors by detuning the resonance frequency of the modes from the qubit frequency. We perform electromagnetic field simulations indicating that the resonance frequency of the modes increases with the number of installed pins and can be engineered to be significantly higher than the highest qubit frequency. We estimate that the error probabilities and decoherence rates due to suitably shifted modes in realistic scenarios can be up to two orders of magnitude lower than the state-of-the-art superconducting qubit error and decoherence rates. Our methods can be extended to different types of packages that do not rely on Pogo pins. Conductive bump bonds, for example, can serve the same purpose in qubit architectures based on flip chip technology. Metalized vias, instead, can be used to mitigate modes due to the increasing size of the dielectric substrate on which qubit arrays are patterned.

arXiv:1710.04590•Quantum Science and Technology•Apr 11, 2018•10 citations

Design and Operation of Wafer-Scale Packages Containing >500 Superconducting Qubits

Oscar W. Kennedy, Waqas Ahmad, Robert Armstrong +14 more

Packages capable of supporting large arrays of high-coherence superconducting qubits are vital for the realisation of fault-tolerant quantum computers and the necessary high-throughput metrology required to optimise fabrication and manufacturing processes. We present a wafer-scale packaging architecture supporting over 500 qubits on a single 3-inch die. The package is engineered to suppress parasitic RF modes, and to mitigate material loss through simulation-informed design while managing differential thermal contraction to ensure robust operation at millikelvin temperatures. System-level heat-load calculations from a large wiring payload show this package may be operated in commercial dilution refrigerators. Measurements of the qubits loaded into the package show median $T_1$, $T_{2e} \sim 100~μ$s ($\sim$100 qubits) alongside readout with median fidelity of 97.5% (54 qubits) and a median qubit temperature of 36 mK (54 qubits). These results validate the performance of these packages and demonstrate that large-scale integration can be achieved without compromising device performance. Finally, we highlight the utility of these packages as a tool for high throughput feedback on qubit figures of merit over large sample sizes, allowing identification of performance outliers in the tails of the coherence distribution, a critical capability for informing fabrication and manufacture of high-quality quantum qubits and quantum processors.

quant-pharXiv:2602.12773•Feb 16, 2026•0 citations

Breaking the scalability barrier via a vertical tunable coupler in 3D integrated transmon system

Xudong Liao, Shuyi Pan, Zhenxing Zhang +11 more

Scaling superconducting quantum processors beyond the constraints of monolithic planar architectures is essential for fault-tolerant quantum computation. Here we demonstrate a three-dimensional (3D) integrated superconducting quantum processor in which two qubit chips are vertically stacked on opposing sides of a carrier chip and galvanically connected via multilayer flip-chip bonding. Intrachip qubit coupling is mediated by planar tunable couplers, whereas interchip coupling is enabled by vertical tunable couplers embedded in the carrier chip. Randomized benchmarking reveals simultaneous single-qubit gate fidelities of 99.87 % with negligible crosstalk, and controlled-Z gates achieve an average fidelity of 97.5 % for both intrachip and interchip operations. We further demonstrate high-fidelity Bell-state preparation and coherent generation of a four-qubit $W$ state, confirming the architecture's capability for interchip entanglement distribution. These results establish vertical coupling as a promising pathway toward scalable quantum processors compatible with advanced quantum error-correcting codes.

quant-pharXiv:2605.11488•May 13, 2026•0 citations

Reworkable Superconducting Qubit Package for Quantum Computing

Rabindra Nath Das, John Cummings, Thomas Hazard +9 more

This paper describes a novel multi-metal layered interconnect-based heterogeneous integration approach for developing a reworkable superconducting qubit package. Various microbump options, including gold, tin, indium, and tin indium, were used to achieve the desired flip-chip configurations. As a case study, we demonstrate a reworkable cryogenic superconducting qubit package capable of interconnecting up to 32 microwave lines. The flip-chip package configurations show low (below 30 dB @ RT) nearest-neighbor crosstalk up to 10 GHz. Initial qubit measurements at low temperatures (~10 mK) show qubit lifetime T1> 100 μs (Q > 2M), which is comparable to the planar versions measured in our standard Al wirebonded package. Keywords—qubit, heterogeneous integration, interconnect, flip-chip, crosstalk.

IEEE Electronic Components and Technology Conference (ECTC)•May 28, 2024•2 citations

Performance characterization of a multi-module quantum processor with static inter-chip couplers

Graham J. Norris, Kieran Dalton, Dante Colao Zanuz +8 more

Abstract Three-dimensional integration technologies such as flip-chip bonding are a key prerequisite to realize large-scale superconducting quantum processors. Modular architectures, in which circuit elements are spread over multiple chips, can further improve scalability and performance by enabling the integration of elements with different substrates or fabrication processes, by increasing the fabrication yield of completed devices, and by physically separating the qubits onto distinct modules to avoid correlated errors mediated by a common substrate. We present a design for a multi-chip module comprising one carrier chip and four qubit modules. Measuring two of the qubits, we analyze the readout performance, finding a mean three-level state-assignment error of $9 \times 10^{-3}$ 9 × 10 − 3 in 200 ns. We calibrate single-qubit gates and measure a mean simultaneous randomized benchmarking error of $6 \times 10^{-4}$ 6 × 10 − 4 , consistent with the coherence times of the qubits. Using a wiring-efficient static inter-module coupler featuring galvanic inter-chip transitions, we demonstrate a controlled-Z two-qubit gate in 100 ns with an error of $7 \times 10^{-3}$ 7 × 10 − 3 extracted from interleaved randomized benchmarking. Three-dimensional integration, as presented here, will continue to contribute to improving the performance of gates and readout as well as increasing the qubit count in future superconducting quantum processors.

EPJ Quantum Technology•Feb 11, 2026•1 citation

Fluxonium qubits in a flip-chip package

Aaron Somoroff, Patrick Truitt, Adam C. Weis +10 more

The strong anharmonicity and high coherence times inherent to fluxonium superconducting circuits are beneficial for quantum information processing. In addition to requiring high-quality physical qubits, a quantum processor needs to be assembled in a manner that minimizes crosstalk and decoherence. In this paper, we report on fluxonium qubits packaged in a flip-chip architecture, where a classical control and readout chip is bump bonded to the quantum chip, forming a multichip module. The modular approach allows for improved connectivity between the qubits and control and readout elements, and separate fabrication processes. We characterize the coherence properties of the individual fluxonium qubits, demonstrate high-fidelity single-qubit gates with 6-ns microwave pulses (without DRAG), and identify the main decoherence mechanisms to improve on the reported results.

arXiv:2303.01481•Physical Review Applied•Feb 7, 2024•11 citations
We demonstrate a pogo pin package for a superconducting quantum processor specifically designed with a nontrivial layout topology (e.g., a center qubit that cannot be accessed from the sides of the chip). Two experiments on two nominally identical superconducting quantum processors in pogo packages, which use commercially available parts and require modest machining tolerances, are performed at low temperature (10 mK) in a dilution refrigerator and both found to behave comparably to processors in standard planar packages with wirebonds where control and readout signals come in from the edges. Single- and two-qubit gate errors are also characterized via randomized benchmarking, exhibiting similar error rates as in standard packages, opening the possibility of integrating pogo pin packaging with extensible qubit architectures.
Abstract A practical quantum computer requires quantum bit (qubit) operations with low error probabilities in extensible architectures. We study a packaging method that makes it possible to address hundreds of superconducting qubits by means of coaxial Pogo pins. A qubit chip is housed in a superconducting box, where both box and chip dimensions lead to unwanted modes that can interfere with qubit operations. We analyze these interference effects in the context of qubit coherent leakage and qubit decoherence induced by damped modes. We propose two methods, half-wave fencing and antinode pinning , to mitigate the resulting errors by detuning the resonance frequency of the modes from the qubit frequency. We perform electromagnetic field simulations indicating that the resonance frequency of the modes increases with the number of installed pins and can be engineered to be significantly higher than the highest qubit frequency. We estimate that the error probabilities and decoherence rates due to suitably shifted modes in realistic scenarios can be up to two orders of magnitude lower than the state-of-the-art superconducting qubit error and decoherence rates. Our methods can be extended to different types of packages that do not rely on Pogo pins. Conductive bump bonds, for example, can serve the same purpose in qubit architectures based on flip chip technology. Metalized vias, instead, can be used to mitigate modes due to the increasing size of the dielectric substrate on which qubit arrays are patterned.
Packages capable of supporting large arrays of high-coherence superconducting qubits are vital for the realisation of fault-tolerant quantum computers and the necessary high-throughput metrology required to optimise fabrication and manufacturing processes. We present a wafer-scale packaging architecture supporting over 500 qubits on a single 3-inch die. The package is engineered to suppress parasitic RF modes, and to mitigate material loss through simulation-informed design while managing differential thermal contraction to ensure robust operation at millikelvin temperatures. System-level heat-load calculations from a large wiring payload show this package may be operated in commercial dilution refrigerators. Measurements of the qubits loaded into the package show median T1T_1T1​, T2e∼100 μT_{2e} \sim 100~μT2e​∼100 μs ($\sim$100 qubits) alongside readout with median fidelity of 97.5% (54 qubits) and a median qubit temperature of 36 mK (54 qubits). These results validate the performance of these packages and demonstrate that large-scale integration can be achieved without compromising device performance. Finally, we highlight the utility of these packages as a tool for high throughput feedback on qubit figures of merit over large sample sizes, allowing identification of performance outliers in the tails of the coherence distribution, a critical capability for informing fabrication and manufacture of high-quality quantum qubits and quantum processors.
Scaling superconducting quantum processors beyond the constraints of monolithic planar architectures is essential for fault-tolerant quantum computation. Here we demonstrate a three-dimensional (3D) integrated superconducting quantum processor in which two qubit chips are vertically stacked on opposing sides of a carrier chip and galvanically connected via multilayer flip-chip bonding. Intrachip qubit coupling is mediated by planar tunable couplers, whereas interchip coupling is enabled by vertical tunable couplers embedded in the carrier chip. Randomized benchmarking reveals simultaneous single-qubit gate fidelities of 99.87 % with negligible crosstalk, and controlled-Z gates achieve an average fidelity of 97.5 % for both intrachip and interchip operations. We further demonstrate high-fidelity Bell-state preparation and coherent generation of a four-qubit WWW state, confirming the architecture's capability for interchip entanglement distribution. These results establish vertical coupling as a promising pathway toward scalable quantum processors compatible with advanced quantum error-correcting codes.
This paper describes a novel multi-metal layered interconnect-based heterogeneous integration approach for developing a reworkable superconducting qubit package. Various microbump options, including gold, tin, indium, and tin indium, were used to achieve the desired flip-chip configurations. As a case study, we demonstrate a reworkable cryogenic superconducting qubit package capable of interconnecting up to 32 microwave lines. The flip-chip package configurations show low (below 30 dB @ RT) nearest-neighbor crosstalk up to 10 GHz. Initial qubit measurements at low temperatures (~10 mK) show qubit lifetime T1> 100 μs (Q > 2M), which is comparable to the planar versions measured in our standard Al wirebonded package. Keywords—qubit, heterogeneous integration, interconnect, flip-chip, crosstalk.
Abstract Three-dimensional integration technologies such as flip-chip bonding are a key prerequisite to realize large-scale superconducting quantum processors. Modular architectures, in which circuit elements are spread over multiple chips, can further improve scalability and performance by enabling the integration of elements with different substrates or fabrication processes, by increasing the fabrication yield of completed devices, and by physically separating the qubits onto distinct modules to avoid correlated errors mediated by a common substrate. We present a design for a multi-chip module comprising one carrier chip and four qubit modules. Measuring two of the qubits, we analyze the readout performance, finding a mean three-level state-assignment error of 9×10−39 \times 10^{-3}9×10−3 9 × 10 − 3 in 200 ns. We calibrate single-qubit gates and measure a mean simultaneous randomized benchmarking error of 6×10−46 \times 10^{-4}6×10−4 6 × 10 − 4 , consistent with the coherence times of the qubits. Using a wiring-efficient static inter-module coupler featuring galvanic inter-chip transitions, we demonstrate a controlled-Z two-qubit gate in 100 ns with an error of 7×10−37 \times 10^{-3}7×10−3 7 × 10 − 3 extracted from interleaved randomized benchmarking. Three-dimensional integration, as presented here, will continue to contribute to improving the performance of gates and readout as well as increasing the qubit count in future superconducting quantum processors.
The strong anharmonicity and high coherence times inherent to fluxonium superconducting circuits are beneficial for quantum information processing. In addition to requiring high-quality physical qubits, a quantum processor needs to be assembled in a manner that minimizes crosstalk and decoherence. In this paper, we report on fluxonium qubits packaged in a flip-chip architecture, where a classical control and readout chip is bump bonded to the quantum chip, forming a multichip module. The modular approach allows for improved connectivity between the qubits and control and readout elements, and separate fabrication processes. We characterize the coherence properties of the individual fluxonium qubits, demonstrate high-fidelity single-qubit gates with 6-ns microwave pulses (without DRAG), and identify the main decoherence mechanisms to improve on the reported results.