Extensible quantum computing architectures require a large array of quantum bits operating with low error rates. A quantum processor based on superconducting devices can be scaled up by stacking microchips that perform wiring, shielding, and computational functionalities. In this article, we demonstrate a vacuum thermocompression bonding technology that utilizes thin indium films as a welding agent to attach pairs of lithographically patterned chips. At 10 mK, we find a specific dc bond resistance of 49.2 μΩ cm2. We show good transmission up to 6.8 GHz in a tunnel-capped, bonded device as compared to a similar uncapped device. Finally, we fabricate and measure a set of tunnel-capped superconducting resonators, demonstrating that our bonding technology can be used in quantum computing applications.
Extensible quantum computing architectures require a large array of quantum bits operating with low error rates. A quantum processor based on superconducting devices can be scaled up by stacking microchips that perform wiring, shielding, and computational functionalities. In this article, we demonstrate a vacuum thermocompression bonding technology that utilizes thin indium films as a welding agent to attach pairs of lithographically patterned chips. At 10 mK, we find a specific dc bond resistance of 49.2 μΩ cm2. We show good transmission up to 6.8 GHz in a tunnel-capped, bonded device as compared to a similar uncapped device. Finally, we fabricate and measure a set of tunnel-capped superconducting resonators, demonstrating that our bonding technology can be used in quantum computing applications.
The superconducting quantum computer is an implementation of the quantum computer and a current leader the field in terms of performance and potential for scalability to large systems. Its two main components are the superconducting microwave resonator and the quantum bit (qubit). In Chapter 1, the concept of quantum computing is introduced, and the superconducting microwave resonator is explained in depth, along with a glimpse at the qubit and a description of two level system loss, the most prominent form of loss in low-power superconducting quantum circuits. Scalability is essential to the development of fault-tolerant quantum computing, as error correction requires a large array of quantum bits. The multilayer quantum circuit architecture is rising to the forefront as a solution to many of the scalability issues facing the field today. Chapter 2 summarizes some of these scalability issues, such as the suppression of unwanted modes and materials losses, and presents an overview of multilayer architectures applied to superconducting quantum circuits. The chapter further delves into indium bump bonding, an essential technique in multilayer circuit fabrication.In Chapter 3, we experimentally demonstrate a thermocompression bonding technology between on-chip indium thin films and apply it to capped superconducting devices. These devices can be used as a building block towards a more scalable architecture: the multilayer quantum circuit. We characterize the dc and microwave performance of these bonded devices at room temperature as well as cryogenic temperatures. At 10 mK, we find a small but significant dc bond resistance of 49.2μΩ cm2. A tunnel-capped, bonded device shows minimal microwave reflections and clean transmission up to 6.8 GHz compared to a similar uncapped device, demonstrating good performance. As a proof of concept, we fabricate and measure a set of tunnel-capped superconducting resonators, demonstrating marginal deterioration in resonator performance due to the bonding procedure. This work demonstrates that thermocompression bonding between thin on-chip indium films is a useful addition to the multilayer quantum circuit toolbox, and that this technique, when applied to form the tunnel-capped superconducting device, shows a promising step towards more scalable architectures. Indium is becoming ubiquitous in superconducting microwave circuits as it continues to be widely adopted as a bonding medium. However, the loss mechanisms in superconducting indium films have not been examined until now. In Chapter 4, we characterize microwave loss in indium and aluminium/indium thin films on silicon substrates by measuring superconducting coplanar waveguide resonators and estimating the main loss parameters at powers down to the sub-photon regime and at temperatures between 10 and 450 mK. We compare films deposited by thermal evaporation, sputtering, and molecular beam epitaxy. We study the effects of heating in vacuum and ambient atmospheric pressure as well as the effects of pre-deposition wafer cleaning using hydrofluoric acid. The microwave measurements are supported by thin film metrology including secondary-ion mass spectrometry. For thermally evaporated and sputtered films, we find that two-level states (TLSs) are the dominating loss mechanism at low photon number and temperature. Thermally evaporated indium is determined to have a TLS loss tangent due to indium oxide of∼5×10−5. The molecular beam epitaxial films show evidence of formation of a substantial indium-silicon eutectic layer, which leads to a drastic degradation in resonator performance.
Flip-chip 3D integration is a key enabling technology for overcoming the routing and layout constraints of planar superconducting quantum processors, but it requires accurate and uniform control of the inter-chip spacing while preserving qubit coherence. In conventional processes, thick indium bumps are deposited symmetrically on both chips, while dedicated spacers are introduced to limit the residual tilt. Here, we present a flip-chip bonding process based on an asymmetric indium architecture, combining 20μm thick indium bumps on the control chip with 200nm thin indium pads on the qubit chip. Using electrical and microwave measurements, we demonstrate low resistance and low loss indium interconnects, and show that transmon qubits integrated with this process reach relaxation and coherence times of T1=(159±14)μs and T2,echo=(294±42)μs, respectively, comparable to planar devices. Combined with a multi angle compression procedure that suppresses systematic tilt, this approach reduces the average post bonding tilt to (20±12)μrad. These results establish an asymmetric indium architecture combined with multi angle compression as a robust, coherence preserving route toward 3D-integrated superconducting quantum processors.
In recent years the interest in building quantum computers with superconducting qubits has steadily increased. Indium is one of the chosen interconnect materials for bonding qubit microchips with Josephson junctions to microelectronic resonators because indium is superconducting and ductile. Indium bump bonding is a common technique for hybridizing pixel radiation sensors to readout chips for some time; however, such detectors operate usually at room temperature. The challenge is to transfer this bonding technique to the fabrication of devices that can operate and withstand very low mKtemperatures. This paper summarizes the current challenges for implementing indium bump bonding to stacked superconducting qubit chips with a particular focus on chip parallelism and superconductivity of the interconnects. A high precision of parallelism between bonded qubit and resonator microchips is essential for minimizing signal loss, and superconducting materials such as indium are required for signal transfer. Photolithography or shadow masking techniques are commonly used to deposit severalμm-thick indium bumps on microchips. This paper outlines initial experiments to verify and optimize the indium bump deposition and flip-chip bonding for superconducting qubit chips. Stacked chip parallelism is evaluated after flip-chip bonding, the tolerance of the parallelism between stacked chips will be determined with an optical scanner, microscope and Scanning Electron Microscopy (SEM). For the superconductivity of interconnects, daisy chain chips are designed, built and flip-chip bonded. The common Under-Bump Metallization (UBM) for the adhesion of indium bumps to pixel pads requires modification with superconductive material and is investigated with resistance measurements that are taken at room temperature with a probe tester and at mK-temperature in a helium dilution refrigerator.
Scalable quantum computing currently requires a large array of qubit integration, but present two-dimensional interconnects face challenges such as wiring congestion, electromagnetic interference, and limited cryogenic space. To overcome this challenge, implementing three-dimensional (3D) vertical architectures becomes crucial. Niobium (Nb), due to its excellent superconducting characteristics and strong fabrication process compatibility, stands out as a prime material choice. The main challenge in Nb-Nb bonding is the presence of an oxide layer at the interface, even after post-bonding annealing across various bonding methods. The native Nb oxide forms rapidly in air, creating a resistive barrier to supercurrent flow and introducing two-level system losses that degrade qubit coherence while increasing the overall thermal budget. These issues show the need for effective surface engineering to suppress oxidation during bonding. This study introduces an ultrathin gold (Au) capping layer as a passivation strategy to prevent oxygen incorporation at the Nb surface. This approach enables low-temperature Nb-Nb thermocompression bonding at 350 °C under a reduced bonding pressure of 0.495 MPa. Detailed microstructural and interfacial analyses confirm that Au passivation effectively suppresses oxide formation and hence enhances bonding uniformity and strength with keeping the superconductivity, establishing a robust route toward low-temperature, low-pressure Nb-Nb bonding for scalable 3D superconducting quantum computing architectures.
3-D chip integration is considered to be the best way for further increasing the number of qubits on chip, and also for integration of qubits and readout electronics. Works have been done to stack two wafers with superconductive interconnections as a demonstration for feasibility of 3-D qubit integration.But all of them use an extra layer of adhesives, indium in particular, to join two neighboring planes.Indium is a good choice of adhesive for wafer bonding at cryogenic temperature. However, there are potential issues to employ this extra layer of adhesive. First, the critical temperature (Tc) of indium being 3.4K means it is suitable preferably for superconducting qubits, but not good enough for qubit implementations or other cryogenic that have above-4K expectations. Second, one general problem in wafer bonding is that alignment is not accurate. Adding an extra layer of anything increases the degree of misalignment. In this work, the extra adhesive layer is abandoned and two wafers are bonded by direct-bonding technique. First, niobium nitride (NbN) is chosen to be the skeleton for this 3-D structure due to its high Tc (18K) as well as its simple composition hence easy fabrication. Sputtering is the method used to fabricate such metal nitride. Sample with Tc=15.6K has been measured so far. Second, both wafer-scale and miniaturized pattern are designed to measure contact resistance of direct bonding of NbN films in room and cryogenic temperature. This work shows the potential of direct-wafer bonding in 3-D chip integration at cryogenic environment, and could further lead to scaling up of quantum processors.
Flip-chip integration offers a promising route toward scalable superconducting quantum processors and hybrid semiconductor-superconductor quantum devices. We develop a three-dimensional transmon architecture using electroplated indium in which the qubit electric field is shared nearly equally between two bump-bonded substrates while maintaining low participation at the indium-bump interface. The resulting geometry is well suited for future hybrid qubits, enabling the integration of distinct material platforms while minimizing sensitivity to bump-interface loss. Using this platform, we evaluate electroplated indium interconnects for superconducting quantum circuits. Flip-chip transmons incorporating electroplated indium bumps exhibit qubit quality factors around 106. In addition, a systematic study of coplanar-waveguide resonators is used to identify losses associated with the electroplating process. In particular, we find that surface losses associated with the gold-layer, used to enable good electric contact with the indium, is likely the primary contributor to the qubit decay rate. These results demonstrate the compatibility of electroplated indium technology with high-coherence superconducting circuits and establish a promising platform for three-dimensional hybrid quantum integration.