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arXiv:1510.03064 · EPJ Quantum Technology

Methodology for bus layout for topological quantum error correcting codes

Martin Wosnitzka, Fabio L Pedrocchi, David Peter Divincenzo

Published Mar 9, 2016• 3 citations
arXivHTMLPDF

Abstract

Most quantum computing architectures can be realized as two-dimensional lattices of qubits that interact with each other. We take transmon qubits and transmission line resonators as promising candidates for qubits and couplers; we use them as basic building elements of a quantum code. We then propose a simple framework to determine the optimal experimental layout to realize quantum codes. We show that this engineering optimization problem can be reduced to the solution of standard binary linear programs. While solving such programs is a NP-hard problem, we propose a way to find scalable optimal architectures that require solving the linear program for a restricted number of qubits and couplers. We apply our methods to two celebrated quantum codes, namely the surface code and the Fibonacci code.

DOI
10.1140/epjqt/s40507-016-0042-8

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Most quantum computing architectures can be realized as two-dimensional lattices of qubits that interact with each other. We take transmon qubits and transmission line resonators as promising candidates for qubits and couplers; we use them as basic building elements of a quantum code. We then propose a simple framework to determine the optimal experimental layout to realize quantum codes. We show that this engineering optimization problem can be reduced to the solution of standard binary linear programs. While solving such programs is a NP-hard problem, we propose a way to find scalable optimal architectures that require solving the linear program for a restricted number of qubits and couplers. We apply our methods to two celebrated quantum codes, namely the surface code and the Fibonacci code.
Quantum computing has raised great interests for its potential to achieve an asymptotic speedup on specific problems. Current quantum devices suffer from noise which needs robust and scalable error-correcting schemes. Topological quantum error correction (TQEC) is among the most promising error-correcting techniques with exponential suppression of error with linear increase of space-time complexity. In this paper, we present the first work to explore space-time optimization between 1-D and 2-D architectures for TQEC circuits. We prove the NP-hardness of the qubit routing problem in the layout synthesis and propose an efficient algorithm to optimize space-time volumes for both 1-D and 2-D qubit architectures with promising experimental results.
This paper investigates the application of topological optimization techniques to quantum error correction codes. The core claim is that optimizing the topological structure of quantum error correction codes can significantly reduce error correction resource consumption and enhance the resilience of quantum computations. This is achieved through the utilization of topological optimization algorithms to identify optimal sub-graph structures within the topological network of a quantum error correction code, minimizing resource usage while maintaining sufficient error correction capability. We present a novel approach to quantum error correction design, moving beyond traditional code selection and offering a framework for dynamic code adaptation. The theoretical framework incorporates concepts from graph theory, linear algebra, and quantum information theory. The primary objective is to demonstrate a method for systematically reducing the overhead associated with quantum error correction, a critical step towards building fault-tolerant quantum computers. Our approach focuses on minimizing the number of physical qubits required to encode a logical qubit, a key metric for evaluating the efficiency of any quantum error correction scheme. The results indicate a substantial potential for optimization, suggesting a path toward more practical and scalable quantum computation.
The fragile nature of quantum information limits our ability to construct large quantities of quantum bits suitable for quantum computing. An important goal, therefore, is to minimize the amount of resources required to implement quantum algorithms, many of which are serial in nature and leave large numbers of qubits idle much of the time unless compression techniques are used. Furthermore, quantum error-correcting codes, which are required to reduce the effects of noise, introduce additional resource overhead. We consider a strategy for quantum circuit optimization based on topological deformation in the surface code, one of the best performing and most practical quantum error-correcting codes. Specifically, we examine the problem of minimizing computation time on a two-dimensional qubit lattice of arbitrary, but fixed dimension, and propose two algorithms for doing so.
Quantum fault tolerance is a prerequisite to harness the full potential of quantum computers. However, achieving fault tolerance remains a major challenge since it requires optimizing tradeoffs between several intertwined theoretical and experimental parameters, including the encoding rate, code distance, parity-check weights, code planarity, and routing. Surface codes remain strong candidates for fault tolerance due to their simple geometric structure, established decoding methods, locality, and experimental attainability. In this work, we present finite families of hyperbolic surface codes that leverage the optimal efficiency scaling kd2/n=C(log⁡k)2kd^2/n = C (\log{k})^2kd2/n=C(logk)2 attainable by surface codes with bounded local geometry. We show that optimizing the periodic identifications can double the code distance and thereby increase the code's efficiency by a factor of four, at fixed qubit count, encoding rate, and parity-check weight. We also address the routing problem of hyperbolic surface codes by introducing a topology-aware algorithm that partitions a hyperbolic code into bounded planar modules while reducing long-range communications demand. Circuit-level Monte Carlo simulations yield finite-size threshold estimates for both modular and monolithic layouts, showing that tripling the long-range gate error probability mildly lowers, but does not eliminate, the estimated error-correction thresholds. Together, these results strengthen the case for hyperbolic surface codes as structured and highly efficient large-scale quantum error correction codes for future fault-tolerant architectures.
Abstract Among the major hardware platforms for large-scale quantum computing, one of the leading candidates is superconducting quantum circuits. Current proposed architectures for quantum error-correction with the promising surface code require a two-dimensional layout of superconducting qubits with nearest-neighbor interactions. A major hurdle for the scalability in such an architecture using superconducting systems is the so-called wiring problem, where qubits internal to a chipset become difficult to access by the external control/readout lines. In contrast to the existing approaches which address the problem through intricate three-dimensional wiring and packaging technology, leading to a significant engineering challenge, here we address this problem by presenting a modified microarchitecture in which all the wiring can be realized through a newly introduced pseudo two-dimensional resonator network which provides the inter-qubit connections via airbridges. Our proposal is completely compatible with current standard planar circuit technology. We carried out experiments to examine the feasibility of the new airbridge component. The measured quality factor of the airbridged resonator is below the simulated surface-code threshold required for a coupling resonator, and it should not limit simulated gate fidelity. The measured crosstalk between crossed resonators is at most −49 dB in resonance. Further spatial and frequency separation between the resonators should result in relatively limited crosstalk between them, which would not increase as the size of the chipset increases. This architecture and the preliminary tests indicate the possibility that a large-scale, fully error-corrected quantum computer could be constructed by monolithic integration technologies without additional overhead or special packaging know-how.
Topological error-correcting codes, such as surface codes and color codes, are promising because quantum operations are realized by two-dimensionally (2D) arrayed quantum bits (qubits). However, physical wiring of electrodes to qubits is complicated, and 3D integration for the wiring requires further development of fabrication technologies. Here, we propose a method to reduce the congestion of wiring to qubits by just adding a swap gate after each controlled-not (cnot) gate. swap gates exchange roles of qubits. Then, the roles of qubits are shared between different qubits. We found that our method transforms the qubit layout and reduces the number of qubits that cannot be two-dimensionally accessed. We show that fully 2D layouts including both qubits and control electrodes can be achieved for surface and color codes of minimum sizes. This method will be beneficial to simplifications of the fabrication process of quantum circuits in addition to improvements in the reliability of qubit systems.