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arXiv:1702.08110 · Physical Review A

Work sharing of qubits in topological error corrections

Tetsufumi Tanamoto, Hayato Goto

Published Aug 28, 2017• 0 citations
arXivHTMLPDF

Abstract

Topological error-correcting codes, such as surface codes and color codes, are promising because quantum operations are realized by two-dimensionally (2D) arrayed quantum bits (qubits). However, physical wiring of electrodes to qubits is complicated, and 3D integration for the wiring requires further development of fabrication technologies. Here, we propose a method to reduce the congestion of wiring to qubits by just adding a swap gate after each controlled-not (cnot) gate. swap gates exchange roles of qubits. Then, the roles of qubits are shared between different qubits. We found that our method transforms the qubit layout and reduces the number of qubits that cannot be two-dimensionally accessed. We show that fully 2D layouts including both qubits and control electrodes can be achieved for surface and color codes of minimum sizes. This method will be beneficial to simplifications of the fabrication process of quantum circuits in addition to improvements in the reliability of qubit systems.

DOI
10.1103/physreva.96.022324

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Topological error-correcting codes, such as surface codes and color codes, are promising because quantum operations are realized by two-dimensionally (2D) arrayed quantum bits (qubits). However, physical wiring of electrodes to qubits is complicated, and 3D integration for the wiring requires further development of fabrication technologies. Here, we propose a method to reduce the congestion of wiring to qubits by just adding a swap gate after each controlled-not (cnot) gate. swap gates exchange roles of qubits. Then, the roles of qubits are shared between different qubits. We found that our method transforms the qubit layout and reduces the number of qubits that cannot be two-dimensionally accessed. We show that fully 2D layouts including both qubits and control electrodes can be achieved for surface and color codes of minimum sizes. This method will be beneficial to simplifications of the fabrication process of quantum circuits in addition to improvements in the reliability of qubit systems.
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The surface code is a prominent topological error-correcting code exhibiting high fault-tolerance accuracy thresholds. Conventional schemes for error correction with the surface code place qubits on a planar grid and assume native CNOT gates between the data qubits with nearest-neighbor ancilla qubits.Here, we present surface code error-correction schemes using only Pauli measurements on single qubits and on pairs of nearest-neighbor qubits. In particular, we provide several qubit layouts that offer favorable trade-offs between qubit overhead, circuit depth and connectivity degree. We also develop minimized measurement sequences for syndrome extraction, enabling reduced logical error rates and improved fault-tolerance thresholds.Our work applies to topologically protected qubits realized with Majorana zero modes and to similar systems in which multi-qubit Pauli measurements rather than CNOT gates are the native operations.
We realize Surface Code quantum memories for nearest-neighbor qubits with always-on Ising interactions. This is done by utilizing multi-qubit gates that mimic the functionality of several gates. The previously proposed Surface Code memories rely on error syndrome detection circuits based on CNOT gates. In a two-dimensional planar architecture, to realize a two-qubit CNOT gate in the presence of couplings to other neighboring qubits, the interaction of the target qubit with its three other neighbors must cancel out. Here we present a new error syndrome detection circuit utilizing multi-qubit parity gates. In addition to speed up in the error correction cycles, in our approach, the depth of the error syndrome detection circuit does not grow by increasing the number of qubits in the logical qubit layout. We analytically design the system parameters to realize new five-qubit gates suitable for error syndrome detection in nearest-neighbor two-dimensional array of qubits. The five-qubit gates are designed such that the middle qubit is the target qubit and all four coupled neighbors are the control qubits. In our scheme, only one control parameter of the target qubits must be adjusted to realize controlled-unitary operations. The gate operations are confirmed with a fidelity of >99.9% in a simulated system consists of nine nearest-neighbor qubits.
Qubit shuttling has become an indispensable ingredient for scaling leading quantum computing platforms, including semiconductor spin, neutral-atom, and trapped-ion qubits, enabling both crosstalk reduction and tighter integration of control hardware. Cai et al. (2023) proposed a scalable architecture that employs short-range shuttling to realize effective three-dimensional connectivity on a strictly two-dimensional device. Building on recent advances in quantum error correction, we show that this architecture enables the native implementation of folded surface codes on 2D hardware, reducing the runtime of all single-qubit logical Clifford gates and logical CNOTs within subsets of qubits from O(d)\mathcal{O}(d)O(d) in conventional surface code lattice surgery to constant time. We present explicit protocols for these operations and demonstrate that access to a transversal SSS gate reduces the spacetime volume of 8T-to-CCZ magic-state distillation by more than an order of magnitude compared with standard 2D lattice surgery approaches. Finally, we introduce a new "virtual-stack" layout that more efficiently exploits the quasi-three-dimensional structure of the architecture, enabling efficient multilayer routing on these two-dimensional devices.
Efforts are being made to develop quantum processors beyond planar connectivity and quantum error correction codes suitable for 3-dimensional structures. In this study, we propose 3-dimensional architectures of logical data qubits and logical ancilla qubits based on surface codes using lattice surgery in situations where 3-dimensional nearest-neighbor connectivity between physical qubits is guaranteed. We also propose a method for performing CNOT operations on the proposed architecture. We present a physical qubit structure that stacks 2-dimensional physical qubit layers and adds several additional physical qubits for lattice surgery between adjacent layers. Our design permits the fast transversal application of CNOT operations between logical qubits in a nearest-neighbor relationship on adjacent layers, which is three times faster than the speed of standard lattice surgery CNOTs. Our design also permits the performance of CNOT operations between logical qubits that are far from each other using fast SWAP operations with transversal CNOT and lattice surgery. To demonstrate the advantages of our architecture, we present the required number of qubits and time for benchmark circuits on the proposed architecture and compare the required qubits and time on the checkerboard architecture and row-type architecture which are a 2-dimensional architectures to show the advantages of our architecture.