Ball-grid array architecture for microfabricated ion traps
Nicholas D. Guise, Spencer D. Fallek, Kelly E. Stevens, Kenneth R. Brown, Curtis Volin, Alexa W. Harter, Jason M. Amini, Robert E. Higashi, Son Thai Lu, Helen M. Chanhvongsak, Thi A. Nguyen, Matthew S. Marcus, Thomas R. Ohnstein, Daniel W. Youngner
State-of-the-art microfabricated ion traps for quantum information research are approaching nearly one hundred control electrodes. We report here on the development and testing of a new architecture for microfabricated ion traps, built around ball-grid array (BGA) connections, that is suitable for increasingly complex trap designs. In the BGA trap, through-substrate vias bring electrical signals from the back side of the trap die to the surface trap structure on the top side. Gold-ball bump bonds connect the back side of the trap die to an interposer for signal routing from the carrier. Trench capacitors fabricated into the trap die replace area-intensive surface or edge capacitors. Wirebonds in the BGA architecture are moved to the interposer. These last two features allow the trap die to be reduced to only the area required to produce trapping fields. The smaller trap dimensions allow tight focusing of an addressing laser beam for fast single-qubit rotations. Performance of the BGA trap as characterized with 40Ca+ ions is comparable to previous surface-electrode traps in terms of ion heating rate, mode frequency stability, and storage lifetime. We demonstrate two-qubit entanglement operations with 171Yb+ ions in a second BGA trap.
State-of-the-art microfabricated ion traps for quantum information research are approaching nearly one hundred control electrodes. We report here on the development and testing of a new architecture for microfabricated ion traps, built around ball-grid array (BGA) connections, that is suitable for increasingly complex trap designs. In the BGA trap, through-substrate vias bring electrical signals from the back side of the trap die to the surface trap structure on the top side. Gold-ball bump bonds connect the back side of the trap die to an interposer for signal routing from the carrier. Trench capacitors fabricated into the trap die replace area-intensive surface or edge capacitors. Wirebonds in the BGA architecture are moved to the interposer. These last two features allow the trap die to be reduced to only the area required to produce trapping fields. The smaller trap dimensions allow tight focusing of an addressing laser beam for fast single-qubit rotations. Performance of the BGA trap as characterized with 40Ca+ ions is comparable to previous surface-electrode traps in terms of ion heating rate, mode frequency stability, and storage lifetime. We demonstrate two-qubit entanglement operations with 171Yb+ ions in a second BGA trap.
Abstract : State-of-the art micro-fabricated ion traps for quantum information research have grown to incorporate upwards of a hundred control electrodes. In the typical architecture, a surface-electrode ion trap is fabricated on a thin chip that sits atop an industry standard CPGA carrier. To supply DC potentials for each electrode, pads on the CPGA are wirebonded to pads on the trap chip, while on-chip surface capacitors suppress pickup from the RF trapping fields. For large numbers of electrodes, the physical area taken up by these wirebonds and filter capacitors present significant constraints for ion trap design and operation. We report here on the development and successful testing of a new architecture for microfabricated ion traps, built around ball-grid array (BGA) connections and trench capacitors. In the BGA trap, through-substrate vias (TSVs) are used to bring electrical signals from the back side of the trap die to the top side. Gold-ball bump bonds connect the back side of the trap die to a separate interposer for signal routing from the CPGA carrier. Trench capacitors fabricated into the trap die eliminate the need for surface capacitors, reducing the trap die area by 30x.
Trapped ions within Paul traps have shown to be a promising architecture in the realisation of a quantum information processor together with the ability of providing quantum simulations. Linear Paul traps have demonstrated long coherence times with ions being well isolated from the environment, single and multi-qubit gates and the high fidelity detection of states. The scalability to large number of qubits, incorporating all the previous achievements requires an array of linear ion traps. Microfabrication techniques allow for fabrication and micron level accuracy of the trap electrode dimensions through photolithography techniques. The first part of this thesis presents the experiential setup and trapping of Yb+ ions needed to test large ion trap arrays. This include vacuum systems that can host advanced symmetric and asymmetric ion traps with up to 90 static voltage control electrodes. Demonstration of a single trapped Yb+ ion within a two-layer macroscopic ion trap is presented. with an ion-electrode distance of 310(10) µm. The anomalous heating rate and spectral noise density of the trap was measured, a main form of decoherence within ion traps. The second half of this thesis presents the design and fabrication of multi-layer asymmetric ion traps. This allows for isolated electrodes that cannot be accessed via surface pathways, allowing for higher density of electrodes as well as creating novel trap designs that allow for the potential of quantum simulations to be demonstrated. These include two-dimensional lattices and ring trap designs in which the isolated electrodes provide more control in the ion position. For the microfabrication of these traps I present a novel high-aspect ratio electroplated electrode design that provides shielding of the dielectric layer. This provides a means to mitigate stray electric field due to charge build up on the dielectric surfaces. Electrical testing of the trap structures was performed to test bulk breakdown and surface flashover of the ion trap architectures. Results showed sufficient isolation between electrodes for both radio frequency and static breakdown. Surface flashover voltage measurements over the dielectric layer showed an improvement of more than double over previous results using a new fabrication technique. This will allow for more powerful ion trap chips needed for the next generation of microfabricated ion trap arrays for scalable quantum technologies.
The advent of microfabricated ion traps for the quantum information community has allowed research groups to build traps that incorporate an unprecedented number of trapping zones. However, as device complexity has grown, the number of digital-to-analog converter (DAC) channels needed to control these devices has grown as well, with some of the largest trap assemblies now requiring nearly one hundred DAC channels. Providing electrical connections for these channels into a vacuum chamber can be bulky and difficult to scale beyond the current numbers of trap electrodes. This paper reports on the development and testing of an in-vacuum DAC system that uses only 9 vacuum feedthrough connections to control a 78-electrode microfabricated ion trap. The system is characterized by trapping single and multiple 40Ca ions. The measured axial mode stability, ion heating rates, and transport fidelities for a trapped ion are comparable to systems with external (air-side) National Instruments PXI-6733 DACs.
Abstract Scaling trapped-ion quantum computing will require robust trapping of at least hundreds of ions over long periods, while increasing the complexity and functionality of the trap itself. Symmetric three-dimensional (3D) structures enable high trap depth, but microfabrication techniques are generally better suited to planar structures that produce less ideal conditions for trapping. We present an ion trap fabricated on stacked eight-inch wafers in a large-scale micro-electro-mechanical system microfabrication process that provides reproducible traps at a large volume. Electrodes are patterned on the surfaces of two opposing wafers bonded to a spacer, forming a 3D structure with 2.5 μm standard deviation in alignment across the stack. We implement a design achieving a trap depth of 1 eV for a 40Ca+ ion held at 200 μm from either electrode plane. We characterize traps, achieving measurement agreement with simulations to within ±5% for mode frequencies spanning 0.6–3.8 MHz, and evaluate stray electric field across multiple trapping sites. We measure motional heating rates over an extensive range of trap frequencies, and temperatures, observing 40 phonons/s at 1 MHz and 185 K. This fabrication method provides a highly scalable approach for producing a new generation of 3D ion traps.
Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. In such context, this thesis is committed to boost the scalability of ion trap by integrating advanced 3D interconnects (e.g., through silicon via) and other functional modules (e.g., silicon photonics and multilayer metallization). 3D interconnects are integrated in the half space underneath surface electrode, to replace conventional wire bonding that extends out of the surface. Silicon photonics (grating coupler and waveguide) in place of bulk optics and lenses are used for on-chip light routing and emission. Multilayer metallization is used to maintain the overall RF performance and enable high-density interconnection where necessary. Firstly, surface electrode ion traps on different substrates (namely high resistivity silicon, silicon with grounding plane and glass) are designed and fabricated. Standard CMOS back-end-of-line fabrication process on 12-inch wafer platform is employed. The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. Due to the incorporation of TSV, the original wire bonding pads as well as the connection circuits on the surface electrodes can be eliminated. As a result, the form factor of TSV integrated trap is reduced by ~10 times. Correspondingly, the parasitic capacitance between neighboring electrodes is reduced from >24 pF to 3 pF. Similarly, the insertion loss of TSV integrated trap drops to 0.11 dB, in sharp comparison to the previous traps on silicon substrates (up to 2.4 dB). Analytical models are built to respectively characterize the electrode capacitance and overall power loss, and a good agreement is achieved between the model and the measurement result. In addition, since TSV is located in the half space underneath the surface electrodes, the electrodes geometry design is enabled with high flexibility. Meanwhile, the laser obstruction issue due to the stick-out bonding wires has been resolved. In terms of the ion trapping performance, both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and the lifetime (~30 minutes) of TSV trap are comparable with non-cryogenic traps of similar dimensions. Moreover, a customized CPGA with patterned redistribution layer is used to locate TSV integrated trap directly in the absence of glass interposer, facilitating high-efficiency thermal management and upgrading the packaging flexibility. At the next stage, the co-integration of other functional modules such as silicon photonics and multilayer metallization with TSV trap is investigated. In silicon photonics module, waveguide and grating coupler are on-chip introduced in place of bulk optics to achieve localized light routing and emission. In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. The deviation between the simulation and measurement is largely due to the fabrication imperfection and the resultant sloped grating coupler profile. This thesis focuses on the scalability enhancement of ion trap by integrating TSV, silicon photonics and multilayer metallization into conventional ion trap. The results are promising and pave the way for the future large scale quantum computing based on trapped ion.
Over the past 15 years ion traps have demonstrated all the building blocks required of a quantum computer. Despite this success, trapping ions remains a challenging task, with the requirement for extensive laser systems and vacuum systems to perform operations on only a handful of qubits. To scale these proof of principle experiments into something that can outperform a classical computer requires an advancement in the trap technologies that will allow multiple trapping zones, junctions and utilize scalable fabrication technologies. I will discuss the construction of an ion trapping experiment, focussing on my work towards the laser stabilization and ion trap design but also covering the experimental setup as a whole. The vacuum system that I designed allows the mounting and testing of a variety of ion trap chips, with versatile optical access and a fast turn around time. I will also present the design and fabrication of a microfabricated Y junction and a 2- dimensional ion trap lattice. I achieve a suppression of barrier height and small variation of secular frequency through the Y junction, aiding to the junctions applicability to adiabatic shuttling operations. I also report the design and fabrication of a 2-D ion trap lattice. Such structures have been proposed as a means to implement quantum simulators and to my knowledge is the first microfabricated lattice trap. Electrical testing of the trap structures was undertaken to investigate the breakdown voltage of microfabricated structures with both static and radio frequency voltages. The results from these tests negate the concern over reduced rf voltage breakdown and in fact demonstrates breakdown voltages significantly above that typically required for ion trapping. This may allow ion traps to be designed to operate with higher voltages and greater ion-electrode separations, reducing anomalous heating. Lastly I present my work towards the implementation of magnetic fields gradients and microwaves on chip. This may allow coupling of the ions internal state to its motion using microwaves, thus reducing the requirements for the use of laser systems.