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arXiv:1303.7127

Hardware Architecture for List SC Decoding of Polar Codes

Alexios Balatsoukas‐Stimming, Alexandre J. Raymond, Warren J. Gross, Andreas Peter Burg

Published Mar 28, 2013• 9 citations
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Abstract

We present a hardware architecture and algorithmic improvements for list SC decoding of polar codes. More specifically, we show how to completely avoid copying of the likelihoods, which is algorithmically the most cumbersome part of list SC decoding. The hardware architecture was synthesized for a blocklength of N = 1024 bits and list sizes L = 2, 4 using a UMC 90nm VLSI technology. The resulting decoder can achieve a coded throughput of 181 Mbps at a frequency of 459 MHz.

DOI
10.48550/arxiv.1303.7127

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We present a hardware architecture and algorithmic improvements for list SC decoding of polar codes. More specifically, we show how to completely avoid copying of the likelihoods, which is algorithmically the most cumbersome part of list SC decoding. The hardware architecture was synthesized for a blocklength of N = 1024 bits and list sizes L = 2, 4 using a UMC 90nm VLSI technology. The resulting decoder can achieve a coded throughput of 181 Mbps at a frequency of 459 MHz.
This brief presents a hardware architecture and algorithmic improvements for list successive cancellation (SC) decoding of polar codes. More specifically, we show how to completely avoid copying of the likelihoods, which is algorithmically the most cumbersome part of list SC decoding. The hardware architecture was synthesized for a block length of N=1024 bits and list sizes L=2, 4 using a UMC 90 nm VLSI technology. The resulting decoder can achieve a coded throughput of 181 Mb/s at a frequency of 459 MHz.
In order to achieve a magnificent error-correcting performance Successive Cancellation List (SCL) decoding is a powerful and excellent method which considers L decoding paths at each decoding stage concurrently. However, the conventional SCL decoder uses L copies of Successive Cancellation (SC) decoder for a list size of L thereby resulting in a massive increase in the hardware as the list size increases which is one of the major drawbacks of SCL decoder. One more drawback of SCL decoder architecture is the long latency of the architecture. Using the proposed efficient utilization of existing hardware architecture, there is a reduction in the number of Merged Processing Elements (MPE) by 39% for a list size of 2 and 45% for a list size of 4 when compared to the existing architectures and a vast reduction compared to conventional SCL decoder. The partial pipelining considered in this work can reduce the latency compared to conventional SCL multi-bit architecture to a greater extent.
Due to its high parallelism, belief propagation (BP) decoding is amenable to high-throughput applications and thus represents a promising solution for the ultra-high peak data rate required by future communication systems. To bridge the performance gap compared to the widely used successive cancellation list (SCL) decoding algorithm, BP list (BPL) decoding for polar codes extends candidate codeword exploration via multiple permuted factor graphs (PFGs) to improve the error-correcting performance of BP decoding. However, it is a significant challenge to design a unified and flexible BPL hardware architecture that supports various PFGs and code configurations. In this paper, we present the first VLSI implementation of a BPL decoder for polar codes that overcomes this implementation challenge with a hardware-friendly algorithm for on-the-fly flexible permutations. First, we introduce a sequential generation (SG) algorithm to obtain a near-optimal PFG set. Additionally, we demonstrate that any permutation can be decomposed into a combination of multiple fixed routings, and design a low-complexity permutation network to generate graphs in an on-the-fly fashion. Our BPL decoder has a low decoding latency by executing decoding and permutation generation in parallel and supports arbitrary list sizes without area overhead. Experimental results based on 28nm FD-SOI technology show that for length-1024 polar codes with a code rate of one-half, our BPL decoder with 32 PFGs exhibits similar error-correcting performance to SCL with a list size of 4 and achieves an average throughput of 25.63 Gbps and an area efficiency of 29.46 Gbps/mm2, which is 1.82× and 4.33× faster than the state-of-the-art BP flip and SCL decoders, respectively
Representing continuous values by streams of random binary bits, stochastic decoding has shown advantages in both hardware efficiency and fault tolerance, therefore has been widely adopted by iterative decoding of error correction codes such as low-density parity-check (LDPC) codes and so on. Recently, polar codes, the first codes that can provably achieve the capacity of symmetric binary-input discrete memoryless channels (B-DMCs), have drawn a lot of attentions from both academia and industry. Although, polar codes with list successive cancellation (SC) decoding can outperform several best-known LDPC codes even within high error-rate regions, the linearly increasing hardware complexity makes its efficient implementation difficult. To this end, the stochastic list SC polar decoding algorithm is proposed in this paper to provide a good tradeoff between performance and complexity. In order to increase the decoding performance of stochastic list SC polar decoder, doubling probability approach is presented. The corresponding hardware architecture is also given. The approximate doubling approach is employed to facilitate the efficient implementation. Implementation results have shown that the proposed stochastic list SC polar decoder can achieve a good trade-off between performance and complexity.
Successive cancellation list (SCL) decoding algorithm is a powerful method that can help polar codes achieve excellent error-correcting performance. However, the current SCL algorithm and decoders are based on likelihood or log-likelihood forms, which render high hardware complexity. In this paper, we propose a log-likelihood-ratio (LLR)-based SCL (LLR-SCL) decoding algorithm, which only needs half the computation and storage complexity than the conventional one. Then, based on the proposed algorithm, we develop low-complexity VLSI architectures for LLR-SCL decoders. Analysis results show that the proposed LLR-SCL decoder achieves 50% reduction in hardware and 98% improvement in hardware efficiency.