Due to its high parallelism, belief propagation (BP) decoding is amenable to high-throughput applications and thus represents a promising solution for the ultra-high peak data rate required by future communication systems. To bridge the performance gap compared to the widely used successive cancellation list (SCL) decoding algorithm, BP list (BPL) decoding for polar codes extends candidate codeword exploration via multiple permuted factor graphs (PFGs) to improve the error-correcting performance of BP decoding. However, it is a significant challenge to design a unified and flexible BPL hardware architecture that supports various PFGs and code configurations. In this paper, we present the first VLSI implementation of a BPL decoder for polar codes that overcomes this implementation challenge with a hardware-friendly algorithm for on-the-fly flexible permutations. First, we introduce a sequential generation (SG) algorithm to obtain a near-optimal PFG set. Additionally, we demonstrate that any permutation can be decomposed into a combination of multiple fixed routings, and design a low-complexity permutation network to generate graphs in an on-the-fly fashion. Our BPL decoder has a low decoding latency by executing decoding and permutation generation in parallel and supports arbitrary list sizes without area overhead. Experimental results based on 28nm FD-SOI technology show that for length-1024 polar codes with a code rate of one-half, our BPL decoder with 32 PFGs exhibits similar error-correcting performance to SCL with a list size of 4 and achieves an average throughput of 25.63 Gbps and an area efficiency of 29.46 Gbps/mm2, which is 1.82× and 4.33× faster than the state-of-the-art BP flip and SCL decoders, respectively
Due to its high parallelism, belief propagation (BP) decoding is amenable to high-throughput applications and thus represents a promising solution for the ultra-high peak data rate required by future communication systems. To bridge the performance gap compared to the widely used successive cancellation list (SCL) decoding algorithm, BP list (BPL) decoding for polar codes extends candidate codeword exploration via multiple permuted factor graphs (PFGs) to improve the error-correcting performance of BP decoding. However, it is a significant challenge to design a unified and flexible BPL hardware architecture that supports various PFGs and code configurations. In this paper, we present the first VLSI implementation of a BPL decoder for polar codes that overcomes this implementation challenge with a hardware-friendly algorithm for on-the-fly flexible permutations. First, we introduce a sequential generation (SG) algorithm to obtain a near-optimal PFG set. Additionally, we demonstrate that any permutation can be decomposed into a combination of multiple fixed routings, and design a low-complexity permutation network to generate graphs in an on-the-fly fashion. Our BPL decoder has a low decoding latency by executing decoding and permutation generation in parallel and supports arbitrary list sizes without area overhead. Experimental results based on 28nm FD-SOI technology show that for length-1024 polar codes with a code rate of one-half, our BPL decoder with 32 PFGs exhibits similar error-correcting performance to SCL with a list size of 4 and achieves an average throughput of 25.63 Gbps and an area efficiency of 29.46 Gbps/mm2, which is 1.82× and 4.33× faster than the state-of-the-art BP flip and SCL decoders, respectively
Owing to its high parallelism, belief propagation (BP) decoding is highly amenable to high-throughput implementations and thus represents a promising solution for meeting the ultra-high peak data rate of future communication systems. However, for polar codes, the error-correcting performance of BP decoding is far inferior to that of the widely used CRC-aided successive cancellation list (SCL) decoding algorithm. To close the performance gap to SCL, BP list (BPL) decoding expands the exploration of candidate codewords through multiple permuted factor graphs (PFGs). From an implementation perspective, designing a unified and flexible hardware architecture for BPL decoding that supports various PFGs and code configurations presents a big challenge. In this paper, we propose the first hardware implementation of a BPL decoder for polar codes and overcome the implementation challenge by applying a hardware-friendly algorithm that generates flexible permutations on-the-fly. First, we derive the graph selection gain and provide a sequential generation (SG) algorithm to obtain a near-optimal PFG set. We further prove that any permutation can be decomposed into a combination of multiple fixed routings, and we design a low-complexity permutation network to satisfy the decoding schedule. Our BPL decoder not only has a low decoding latency by executing the decoding and permutation generation in parallel, but also supports an arbitrary list size without any area overhead. Experimental results show that, for length-1024 polar codes with a code rate of one-half, our BPL decoder with 32 PFGs has a similar error-correcting performance to SCL with a list size of 4 and achieves a throughput of 25.63 Gbps and an area efficiency of 29.46 Gbps/mm2 at SNR=4.0dB, which is 1.82× and 4.33× faster than the state-of-the-art BP flip and SCL decoders,~respectively
We propose a belief propagation list (BPL) decoder with comparable performance to the successive cancellation list (SCL) decoder of polar codes, which already achieves the maximum likelihood (ML) bound of polar codes for sufficiently large list size L. The proposed decoder is composed of multiple parallel independent belief propagation (BP) decoders based on differently permuted polar code factor graphs. A list of possible transmitted codewords is generated and the one closest to the received vector, in terms of Euclidean distance, is picked. To the best of our knowledge, the proposed BPL decoder provides the best performance of plain polar codes under iterative decoding known so far. The proposed algorithm does not require any changes in the polar code structure itself, rendering the BPL into an alternative to the SCL decoder, equipped with a soft output capability enabling, e.g., iterative detection and decoding to further improve performance. Further benefits are the lower decoding latency than the SCL decoder and the possibility of high throughput implementations. Additionally, we show that a different selection strategy of frozen bit positions can further enhance the error-rate performance of the proposed decoder.
Recently, belief propagation list (BPL) decoding has been proposed to achieve the excellent parallel decoding performance of polar codes with high throughput and low latency. However, the performance gap between BPL decoding and state-of-the-art successive cancellation list (SCL) decoding is still significant at practical SNRs. In this letter, we propose an efficient BPL flip (EBPLF) decoding algorithm for filling this gap. Firstly, an efficient bit-flipping strategy under BPL decoding is proposed to allow multiple bits being flipped more efficiently than the existing bit-flipping strategy. Then, by exploiting the decoding diversity and reliability of each bit over the multiple factor graphs within BPL decoding, an enhanced flip set is constructed to identify the error-prone patterns in an efficient way. Extensive simulation results show that EBPLF decoding outperforms the existing BPLF scheme and approaches the performance of adaptive SCL decoding at practical SNRs with much lower average latency.
Since the inherent serial nature of successive cancellation list (SCL) decoding results in a long latency, belief propagation (BP) decoding for polar codes has drawn attention for high-throughput applications. However, its error correction performance is inferior to that of SCL decoding. Therefore, the bit-flipping strategy has been recently applied to BP decoding, which can approach the SCL decoding performance through multiple additional decoding attempts. The original BP flip (BPF) decoding suffers from an inaccurate identification of erroneous bits by a fixed flip set (FS), which has been improved by the generalized BPF (GBPF) decoding. In this article, the GBPF decoding is extended to support multiple bits being flipped in one decoding attempt. In addition, for two types of decoding errors: detected errors and undetected errors, we propose two novel methods to more effectively identify erroneous bits. For detected errors, the concept of loop sets is defined and a loopbased identification method is introduced based on the study of error patterns of BP decoding. On the other hand, a method to generate a more accurate fixed FS is proposed for undetected errors, which considers the bit error distribution under BP decoding. Combining the two methods, the GBPF with merged sets (GBPF-MS) decoding can achieve the SCL-8 performance and outperforms the state-of-the-art BPF, BP list, and SC flip (SCF) decoding, for polar codes with length 1024 and information rate 1/2. Implemented by 40nm CMOS technology, the proposed GBPF-MS decoder with ten flips exhibits an average throughput of 4.19 Gbps at 2.5 dB, which is 1.6× and 1.72× faster than the state-of-the-art SCL-4 and SCF decoders, respectively.
Polar codes have become the channel coding scheme for control channel of enhanced mobile broadband in the 5G communication systems. Belief propagation (BP) decoding of polar codes has advantages of low decoding latency and high parallelism but achieves worse bit error ratio (BER) performance compared with the successive cancellation list (SCL) decoding scheme. In this paper, an improved BP list (IBPL) decoding algorithm is proposed with comparable BER performance to SCL algoritm. Firstly, the optimal permuted factor graph is analyzed for polar codes, which improves the performance of the BP decoder without path extension. Furthermore, based on the optimal graph, the bit metric and decoding path metric are proposed to extend and prune the decoding path. The proposed IBPL decoder is focused on not only the permutation of polar codes but also the reliabilities of decoded codewords during each iteration of BP decoding, which has a more accurate decoding path list. The simulation results show that the proposed IBPL decoder improves the BER performance compared with the original BP decoder significantly, and can approach the performance of the SCL decoder at low signal to noise ratio regions.
In this paper, we present an improved belief propagation list (BPL) decoding algorithm for polar codes. Rather than getting L factor graphs (FGs) at random and cyclic shift permutation, we use the upper bounds on the block error propability of polar codes with different FGs as the metric to choose the best L FGs. By observing the bounds of different FGs, we propose a heuristic method to reduce search complexity. Simulation results show that there is only a gap of 0.2 dB between the frame error rate (FER) performance of the improved BPL decoder using RM16-GA construction and that of length-1024 5G polar code decoded by SCL with the same list size of 32 at FER =10-4. Moreover, with the proposed FG selection method, BPL decoding can reduce clock cycles by 97.74% compared with the SCL decoding.