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International SoC Design Conference

Hybrid Decoding for Polar Codes

Soyeon Choi, Hoyoung Yoo

Published Nov 1, 2018• 2 citations
Publisher

Abstract

Among various polar decoding algorithms, SC-List [2] and SC-Flip [3] suffer from high hardware complexity and long decoding latency, respectively. In this paper, a novel hybrid decoding algorithm is proposed to achieve affordable hardware complexity with a suitable decoding latency. According to the experimental results, the proposed method affords a comparable error-correcting performance to that of SC-List [2] and SC-Flip [3] counter parts.

DOI
10.1109/isocc.2018.8649922

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Among various polar decoding algorithms, SC-List [2] and SC-Flip [3] suffer from high hardware complexity and long decoding latency, respectively. In this paper, a novel hybrid decoding algorithm is proposed to achieve affordable hardware complexity with a suitable decoding latency. According to the experimental results, the proposed method affords a comparable error-correcting performance to that of SC-List [2] and SC-Flip [3] counter parts.
There are two main algorithms, successive cancellation (SC) algorithm and brief propagation (BP) algorithm, for decoding polar code. The SC algorithm has better error-correcting performance and the BP algorithm has low latency. The hybrid BP-SC decoding combines these two decoding algorithms and achieves improvements. Furthermore, the successive cancellation flip (SCF) algorithm improves the error-correcting performance for the SC algorithm, but it has higher computation complexity and latency. Based on the hybrid BP-SC decoding, we proposed a hybrid BP-SC/SCF decoding for polar codes in this paper to further improve the error-correcting performance. The result shows our approach outperforms to frame error rates (FER) of the SC decoding and BP decoding at least 0.5-dB and outperforms hybrid BP-SC decoding by 0.2-dB to 0.4-dB. Compared with the SCF decoding, the hybrid BPSC/SCF decoding has a small degradation of FER in a highquality channel but it significantly reduces the average computation complexity.
By adopting successive cancellation list decoding (SCL), polar codes demonstrate competitive error correction performance over LDPC and Turbo codes. However, SCL decoding suffers from high computational complexity and long decoding latency, especially when the list size is very large. Successive cancellation flip (SCF), as another decoding algorithm that can achieve high error correction performance, has a complexity that is close to that of successive cancellation (SC) decoding. With the observation that SCL and SCF decoding are similar at giving more chances to inspect possible codewords simultaneously or sequentially, a novel hybrid decoder is proposed in this paper, which essentially combines the ideas of SCF and SCL decoders. Moreover, in order to compensate for the degradation of performance caused by the reduction of path splitting and further reduce the decoding latency, the convolutional polar codes are adopted with a designed bit-flipping set. Simulation results demonstrate that the proposed decoder achieves the reduction of decoding latency while attaining better performance than conventional CRC-aided SCL decoder.
SC-Flip (SCF) decoding is a low-complexity polar code decoding algorithm alternative to SC-List (SCL) algorithm with small list sizes. To achieve the performance of the SCL algorithm with large list sizes, the Dynamic SC-Flip (DSCF) algorithm was proposed. However, DSCF involves logarithmic and exponential computations that are not suitable for practical hardware implementations. In this work, we propose a simple approximation that replaces the transcendental computations of DSCF decoding. Moreover, we show how to incorporate fast decoding techniques with the DSCF algorithm. With proposed approaches, the computational complexity of DSCF decoding is remarkably reduced while maintaining equivalent decoding performance.
Benefiting from performance advantages under short code lengths, polar codes are well-suited for certain scenarios, such as the future Internet of Things (IoT) applications that require high reliability and low power. Existing list flip decoders can efficiently further enhance the error-correction performance of polar codes with finite code lengths, particularly the dynamic successive cancellation list flip (D-SCLF) decoder with flexible high-order error-correction capability (FHECC). However, to the best of our knowledge, current list flip decoders cannot effectively balance complexity and error-correction efficiency. To address this, we propose a parity-check-aided D-SCLF (PC-DSCLF) decoder. This decoder, based on FHECC and the characteristics of the list flip decoding process, introduces a simplified flip metric and a hybrid check scheme, along with a decoding method that supports the check scheme, enabling it to retain FHECC while achieving low complexity. Simulation results show that the proposed PC-DSCLF decoder achieves up to a 51.1\% average complexity reduction compared to the D-SCLF algorithm with distributed CRC for PC(512,256+24)PC(512, 256+24)PC(512,256+24)
Successive cancellation flip (SCFlip) decoding with flipping characteristic can significantly improve the decoding performance of polar codes by taking the advantage of extra decoding attempts. Therefore, we propose a new Fano-SC-Flip decoding algorithm of polar codes, which integrates the flip feature into the Hybrid (Fano-SC) algorithm. By comparing both the modeling and the genuine complexity, we obtain the applicable conditions where using the Hybrid-Flip decoder is relatively cost-effective with the trade-off between the complexity and error correction performance. Finally, the optimal flip allocation strategy is found and adaptively adjusted for each given SNR, by using the proportion of errors in each segment based on the oracle-assisted SC (OA-SC) decoder.
A new permutation decoding approach for polar codes is presented. The proposed decoder can be used to achieve the error correction performance of a successive cancellation list (SCL) decoder, while it can either improve latency of the SCL decoder or decrease its hardware complexity. As opposed to the SCL algorithm, the proposed permutation algorithm can be implemented without sorting operation. It is shown that the error correction performance of the algorithm is similar to that of the SCL decoder for polar codes. Moreover, a new construction aiming to improve the error correction performance of polar codes under the proposed algorithm is presented.