Reciprocal quantum logic combines the speed and power-efficiency of single-flux quantum superconductor devices with design features that are similar to CMOS. We have demonstrated an 8-bit carry look-ahead adder in the technology using combinational gates with fanout of four and non-local interconnect. Measured power dissipation of the fully active circuit is only 510 nW at 6.2 GHz. Latency is only 150 ps at a clock rate of 10 GHz.
Reciprocal quantum logic combines the speed and power-efficiency of single-flux quantum superconductor devices with design features that are similar to CMOS. We have demonstrated an 8-bit carry look-ahead adder in the technology using combinational gates with fanout of four and non-local interconnect. Measured power dissipation of the fully active circuit is only 510 nW at 6.2 GHz. Latency is only 150 ps at a clock rate of 10 GHz.
Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. In this paper, we conducted the high-frequency operation and energy measurement of an AQFP circuit with more than 1000 Josephson junctions in the experiment. We designed an 8-bit carry look-ahead adder (CLA) using AQFP gates and fabricated it using an advanced fabrication technology, the AIST 10 kA/cm2 Nb high-speed standard process. The correct operation of the 8-bit CLA was demonstrated at a 1-GHz clock frequency for a critical carry propagation test vector. The energy dissipation of the 8-bit CLA was measured by observing the power of excitation current. Our results showed that the energy dissipation per operation of the 8-bit CLA can be estimated to be approximately 1.5 aJ, or 24kBT per junction, where kB is the Boltzmann constant and T is the operating temperature.
We have developed a new superconducting digital technology, Reciprocal Quantum Logic, that uses ac power carried on a transmission line, which also serves as a clock. Using simple experiments, we have demonstrated zero static power dissipation, thermally limited dynamic power dissipation, high clock stability, high operating margins, and a low bit-error rate. These features indicate that the technology is scalable to far more complex circuits at a significant level of integration. On the system level, Reciprocal Quantum Logic combines the high speed and low-power signal levels of single-flux-quantum signals with the design methodology of semiconductor digital logic, including low static power dissipation, low latency combinational logic, and efficient device count.
We have designed, fabricated and experimentally demonstrated an 8-bit carry look-ahead adder using clockless AND and NIMPLY cells. A clockless cell is a logic cell without a clock input. Comprared to the circuit using only clocked cells, the circuit using clockless cells has fewer routing wires and splitters. Decrease of the numbers of wires and splitters can reduce the area of a circuit. The 8-bit adder core (without SFQ-to-DC and DC-to-SFQ converters, the clock generator and input and output shift registers for the high frequency test) has 3320 Josephson junctions (JJs) occupying the area of 1.84 mm2. It is designed for the target operation frequency is 10 GHz with 3 pipeline stages, and the delay from the clock input to the primary outputs of 74 ps at most at the bias voltage of 2.5 mV. The adder chip was fabricated using AIST 10-kA/cm2 Advanced Process (ADP2) and tested at low and high frequency with measured bias margins of +16%/+6%. The measured maximum frequency was 12.87 GHz.
Complimentary Medal-Oxide Semiconductor (CMOS) technology is expected to soon reach its fundamental limits of operation. The fundamental speed limit of about 4 GHz has already effectively been sidestepped by parallelization. This increases raw processing power but does nothing to improve power dissipation or latency. One approach for increasing computing performance involves using superconducting digital logic circuits. In this thesis I describe a new kind of superconducting logic, invented by Quentin Herr at Northrop Grumman, which uses reciprocal pairs of quantized single magnetic flux pulses to encode classical bits. In Reciprocal Quantum Logic (RQL) the data is encoded in integer units of the magnetic flux quantum. RQL gates operate without the bias resistors of previous superconducting logic families and dissipate several orders of magnitude less power. I demonstrate the basic operation of key RQL gates (AndOr, AnotB, Set/Reset) and show their self-resetting properties. Together, these gates form a universal logic set and provide memory capabilities. Experiments measuring the bit error rate of the AndOr gate extrapolated a minimum BER of 10−480 and a BER of 10−44 with 30% margins on flux biasing. I describe an analytic timing model for RQL gates which demonstrates the self-correcting timing features. From this model I derive equations for the timing behavior and operating limits. Using this timing model I ran simulations to determine correction factions for more accurate predictions at higher frequencies. Using these results, I also develop Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) models to describe the combinational logic of RQL gates. To test the timing predictions of the timing model, I performed three experiments on Nb/AlOx/Nb circuits at 4.2 K. The first measured the time of output. The second measured the operating margins of the circuit. The third measured the maximum frequency of operation for RQL circuits. Together, these three experiments showed quantitative agreement with the model for the timing output, qualitative agreement with the limits of operation, and a projected speed limit of 50 GHz for the Hypres 4.5 kA/cm2 process. To power RQL circuits I describe a new design for power splitters and combiners which minimize standing waves. I describe a new kind of Wilkinson power splitter which required numerical optimization but proved to be adequate. I experimentally tested two new designs of the power splitter. Both showed less than 10% variation in standing waves between power splitter and combiner, making it adequate for RQL circuits. I also compared these results with the S-parameters of the power network, which also indicated that the design was adequate for RQL circuits. Finally, I tested an 8-bit Kogge-Stone architecture carry-look ahead adder designed using VHDL models. The adder contained 815 Josephson junctions and was fully functional at 6.21 GHz with a latency of 1.25 clock cycles. The adder produced the correct logical output, had a measured optimal operating point within 8% of the optimal simulated operating point, and measured power margins of 1 dB. It operated best at the designed clock amplitude of 0.88 Ic and dissipated 0.570 mW of power.
Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family that can operate with low switching energy due to adiabatic switching. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current. We demonstrated several AQFP logic gates with delay-line clocking and demonstrated a phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. In the present study, we design and demonstrate an AQFP 8-bit ripple carry adder with delay-line clocking to show that delay-line clocking and the phase skipping operation are applicable to large-scale AQFP circuits. The latency of this adder is 960 ps, which is 40% of that for a conventional design. Moreover, due to the phase skipping operation, the junction count is reduced to approximately 70% of that for the conventional design. We find that this adder can operate at up to 4 GHz. The above results indicate that large-scale AQFP circuits can operate with low latency and low junction count by using delay-line clocking and a phase skipping operation.
Reversible logic has represented itself as a prominent technology which plays an important role in Quantum Computing. Theoretically Quantum Computers operates at high speed and consumes less power. Furthermore, Reversible logic can break the conventional speed of power trade-off. To prove this we are implementing Ripple Carry Adder and Carry Look Ahead Adder using reversible logic gates. The paper presents efficient adder circuits using Peres gate, New fault Tolerant gate and Double Feyman gate. The complexity, simulated outputs and the speed parameters for the adder circuit have been indicated using the Quartus II 9.1 edition and Modelsim tool. Moreover, the quantum algorithms can potentially solve NP-complete problems. Furthermore, doing high performance functions beyond the limit of deterministic computer systems is possible by only reversible logic. Quantum operations are unitary in nature which is reversible and hence the arithmetic operations like adders can be implemented using the reversible logic. Likewise, optimized block size, minimum ancillary bits, and one to one mappings of inputs and outputs are obtained in the reversible adder circuit, giving fan out as 1. Hence, the Ripple Carry Adder and Carry look Ahead Adder is providing complexity reduction and high speed, proving to be an efficient and important part in the development of arithmetic blocks of Quantum Computers.