Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

arXiv:1010.5449 · IEEE Transactions on Applied Superconductivity

Diffusion Stop-Layers for Superconducting Integrated Circuits and Qubits With Nb-Based Josephson Junctions

Sergey K. Tolpygo, Denis Amparo, Richard T. Hunt, John A. Vivalda, Daniel T. Yohannes

Published Dec 9, 2010• 15 citations
arXivHTMLPDF

Abstract

New technology for superconductor integrated circuits has been developed and is presented. It employs diffusion stop-layers (DSLs) to protect Josephson junctions (JJs) from interlayer migration of impurities, improve JJ critical current (Ic) targeting and reproducibility, eliminate aging, and eliminate pattern-dependent effects in Icand tunneling characteristics of Nb/Al/AlOx/Nb junctions in integrated circuits. The latter effects were recently found in Nb-based JJs integrated into multi layered digital circuits. E.g., it was found that Josephson critical current density (Jc) may depend on the JJ's environment, on the type and size of metal layers making contact to niobium base (BE) and counter electrodes (CE) of the junction, and also change with time. Such Jcvariations within a circuit reduce circuit performance and yield, and restrict integration scale. This variability of JJs is explained as caused by hydrogen contamination of Nb layers during wafer processing, which changes the height and structural properties of AlOxtunnel barrier. Redistribution of hydrogen impurities between JJ electrodes and other circuit layers by diffusion along Nb wires and through contacts between layers causes long-term drift of Jc. At least two DSLs are required to completely protect JJs from impurity diffusion effects-right below the junction BE and right above the junction CE. The simplest and the most technologically convenient DSLs we have found are thin (from ~3 nm to ~10 nm) layers of Al. They were deposited in-situ under the BE layer, thus forming an Al/Nb/Al/AlOx/Nb penta-layer, and under the first wiring layer to junctions' CE, thus forming an Al/Nb wiring bi-layer. A significant improvement of Jcuniformity on 150-mm wafer has also been obtained along with large improvements in Jctargeting and run-to-run reproducibility.

DOI
10.1109/tasc.2010.2089665

Related papers

Development of Self-Shunted Josephson Junctions for a Ten-Superconductor-Layer Fabrication Process: Nb/NbN x /Nb Junctions

Sergey K. Tolpygo, Ravi Rastogi, Terence J. Weir +2 more

To increase the integration scale of superconductor electronics, we are developing a new node, titled SFQ7ee, of the fabrication process at MIT Lincoln Laboratory. In comparison to the existing SFQ5ee node, we increased the number of fully planarized superconducting layers to ten and utilized NbN and NbN/Nb kinetic inductors to increase the possible inductor number density above a hundred million inductors per cm2. Increasing the Josephson junction number density to the same level requires implementing self-shunted high-JcJosephson junctions. We investigated the properties of Nb/NbNx/Nb trilayer junctions as a potential replacement of high-JcNb/Al-AlOx/Nb junctions, where NbNxis a disordered, overstoichiometric, nonsuperconducting nitride deposited by reactive sputtering. Dependences of theIcRnproduct and Josephson critical current density, Jc on the NbNx barrier thickness and temperature were studied in the thickness range from 5 nm to 20 nm. The fabricated junctions can be well described by the microscopic theory of SNS junctions, assuming no suppression of the energy gap in Nb electrodes near the NbNxinterfaces and a Cooper pair decay length in the NbNx barrier, ξnTcof about 2.3 nm. Current-voltage characteristics of the junctions are well described by the resistively and capacitively shunted junction (RCSJ) model without excess current. In the studied rangeJc2, the Nb/NbNx/Nb junctions have lower values of the specific resistanceRnA, lower IcRn products, and a stronger dependence of theIcRnon temperature than the self-shunted or critically damped externally shunted Nb/Al-AlOx/Nb junctions with the same critical current density; A is the junction area,Icthe junction critical current, and Rnthe effective shunting resistance.

IEEE Transactions on Applied Superconductivity•Feb 9, 2024•12 citations

Development of Multi-Layer Fabrication Process for SFQ Large Scale Integrated Digital Circuits

Liliang Ying, Xue Zhang, Minghui Niu +4 more

We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO2films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistanceRshof 2 Ω, followed by the deposition of Nb/Al-AlOx/Nb trilayer Josephson-junction. The target critical current densityJcwas set at 6 kA/cm2. Small-scale circuits such as our standard library cells have been successfully fabricated and tested, confirming the capability of our fabrication technology for superconducting integrated circuits.

arXiv:2011.06272•IEEE Transactions on Applied Superconductivity•Mar 11, 2021•76 citations

Fabrication And Characterization Of High-Quality Nb/Al-AlO$_x$/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques

Alexander Stoll, Andreas Reifenberger, Daniel Hengstler +2 more

Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO$_2$ to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO$_2$. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over $90\,\%$ on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to $1\,\mathrm{μm} \times 1\,\mathrm{μm}$ distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.

arXiv:2609.08569•Aug 26, 2026•0 citations

Development of 15kA/cm$^2$ Fabrication Process for Superconducting Integrated Digital Circuits

Liliang Ying, Xue Zhang, Guixiang He +7 more

A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated "SIMIT Nb03" process and Chemical Mechanical Planarization (CMP) technology. Seven Nb superconducting layers and one Mo resistor layer are included in the "SIMIT Nb04" process with 19 mask levels. The device structure is composed of active layers including junctions at the bottom, two passive transmission line (PTL) layers in the middle and a DC power layer at the top. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 3 $Ω$, followed by the deposition of Nb/Al-AlO$_x$/Nb trilayer Josephson-junction with a target critical current density Jc at 15 kA/cm$^2$. To increase the Al-AlO$_x$ barrier layer etching's repeatability, an additional barrier protection layer was applied. To accomplish high-quality planarization, we created a planarization procedure coupled with dummy filling. To assess the process dependability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and monitored. The successful manufacturing and testing of a few small-scale circuits, like our standard library cells, further attests to the viability of our fabrication process for superconducting integrated circuits.

arXiv:2304.01588•Apr 4, 2023•0 citations

Fabrication Process of Planarized Multi-Layer Nb Integrated Circuits

T. Satoh, K. Hinode, Hiroyuki Akaike +3 more

To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NEC's standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.

IEEE Transactions on Applied Superconductivity•Jun 1, 2005•42 citations

Overdamped Josephson junctions with Nb/AlOx/Al/AlOx/Nb structure for integrated circuit application

Masaaki Maezawa, Akira Shoji

We present characteristics of overdamped Josephson junctions consisting of Nb/AlOx/Al/ AlOx/Nb structures. The junctions were fabricated using a well-developed Nb/AlOx/Nb-junction technology and showed well-defined Josephson characteristics at 4.2 K. The characteristic voltage Vc [the product of the critical current Ic and the effective normal resistance Rn(eff)] of junctions, which determines high-frequency performance of the junction, was in the range of 0.1–0.5 mV, and the critical current density Jc in the range of 102–104 A/cm2. Maximum-to-minimum variations in Ic over a wafer were ±4% for junctions with Vc=0.15 mV and ±13% for junctions with Vc=0.5 mV.

Applied Physics Letters•Jun 30, 1997•68 citations
New technology for superconductor integrated circuits has been developed and is presented. It employs diffusion stop-layers (DSLs) to protect Josephson junctions (JJs) from interlayer migration of impurities, improve JJ critical current (Ic) targeting and reproducibility, eliminate aging, and eliminate pattern-dependent effects in Icand tunneling characteristics of Nb/Al/AlOx/Nb junctions in integrated circuits. The latter effects were recently found in Nb-based JJs integrated into multi layered digital circuits. E.g., it was found that Josephson critical current density (Jc) may depend on the JJ's environment, on the type and size of metal layers making contact to niobium base (BE) and counter electrodes (CE) of the junction, and also change with time. Such Jcvariations within a circuit reduce circuit performance and yield, and restrict integration scale. This variability of JJs is explained as caused by hydrogen contamination of Nb layers during wafer processing, which changes the height and structural properties of AlOxtunnel barrier. Redistribution of hydrogen impurities between JJ electrodes and other circuit layers by diffusion along Nb wires and through contacts between layers causes long-term drift of Jc. At least two DSLs are required to completely protect JJs from impurity diffusion effects-right below the junction BE and right above the junction CE. The simplest and the most technologically convenient DSLs we have found are thin (from ~3 nm to ~10 nm) layers of Al. They were deposited in-situ under the BE layer, thus forming an Al/Nb/Al/AlOx/Nb penta-layer, and under the first wiring layer to junctions' CE, thus forming an Al/Nb wiring bi-layer. A significant improvement of Jcuniformity on 150-mm wafer has also been obtained along with large improvements in Jctargeting and run-to-run reproducibility.
To increase the integration scale of superconductor electronics, we are developing a new node, titled SFQ7ee, of the fabrication process at MIT Lincoln Laboratory. In comparison to the existing SFQ5ee node, we increased the number of fully planarized superconducting layers to ten and utilized NbN and NbN/Nb kinetic inductors to increase the possible inductor number density above a hundred million inductors per cm2. Increasing the Josephson junction number density to the same level requires implementing self-shunted high-JcJosephson junctions. We investigated the properties of Nb/NbNx/Nb trilayer junctions as a potential replacement of high-JcNb/Al-AlOx/Nb junctions, where NbNxis a disordered, overstoichiometric, nonsuperconducting nitride deposited by reactive sputtering. Dependences of theIcRnproduct and Josephson critical current density, Jc on the NbNx barrier thickness and temperature were studied in the thickness range from 5 nm to 20 nm. The fabricated junctions can be well described by the microscopic theory of SNS junctions, assuming no suppression of the energy gap in Nb electrodes near the NbNxinterfaces and a Cooper pair decay length in the NbNx barrier, ξnTcof about 2.3 nm. Current-voltage characteristics of the junctions are well described by the resistively and capacitively shunted junction (RCSJ) model without excess current. In the studied rangeJc2, the Nb/NbNx/Nb junctions have lower values of the specific resistanceRnA, lower IcRn products, and a stronger dependence of theIcRnon temperature than the self-shunted or critically damped externally shunted Nb/Al-AlOx/Nb junctions with the same critical current density; A is the junction area,Icthe junction critical current, and Rnthe effective shunting resistance.
We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO2films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistanceRshof 2 Ω, followed by the deposition of Nb/Al-AlOx/Nb trilayer Josephson-junction. The target critical current densityJcwas set at 6 kA/cm2. Small-scale circuits such as our standard library cells have been successfully fabricated and tested, confirming the capability of our fabrication technology for superconducting integrated circuits.
Fabrication And Characterization Of High-Quality Nb/Al-AlOx_xx​/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO2_22​ to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO2_22​. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over 90 %90\,\%90% on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to 1 μm×1 μm1\,\mathrm{μm} \times 1\,\mathrm{μm}1μm×1μm distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
Development of 15kA/cm2^22 Fabrication Process for Superconducting Integrated Digital Circuits
A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated "SIMIT Nb03" process and Chemical Mechanical Planarization (CMP) technology. Seven Nb superconducting layers and one Mo resistor layer are included in the "SIMIT Nb04" process with 19 mask levels. The device structure is composed of active layers including junctions at the bottom, two passive transmission line (PTL) layers in the middle and a DC power layer at the top. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 3 ΩΩΩ, followed by the deposition of Nb/Al-AlOx_xx​/Nb trilayer Josephson-junction with a target critical current density Jc at 15 kA/cm2^22. To increase the Al-AlOx_xx​ barrier layer etching's repeatability, an additional barrier protection layer was applied. To accomplish high-quality planarization, we created a planarization procedure coupled with dummy filling. To assess the process dependability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and monitored. The successful manufacturing and testing of a few small-scale circuits, like our standard library cells, further attests to the viability of our fabrication process for superconducting integrated circuits.
To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NEC's standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.
We present characteristics of overdamped Josephson junctions consisting of Nb/AlOx/Al/ AlOx/Nb structures. The junctions were fabricated using a well-developed Nb/AlOx/Nb-junction technology and showed well-defined Josephson characteristics at 4.2 K. The characteristic voltage Vc [the product of the critical current Ic and the effective normal resistance Rn(eff)] of junctions, which determines high-frequency performance of the junction, was in the range of 0.1–0.5 mV, and the critical current density Jc in the range of 102–104 A/cm2. Maximum-to-minimum variations in Ic over a wafer were ±4% for junctions with Vc=0.15 mV and ±13% for junctions with Vc=0.5 mV.