In this paper we present the design, modeling, and experimental testing of surface electrode ion traps fabricated in a heterostructure configuration comprising a silicon substrate, silicon dioxide insulators, and aluminum electrodes. This linear trap has a geometry with symmetric RF leads, two interior DC electrodes, and 40 individual lateral DC electrodes. Plasma enhanced chemical vapor deposition (PECVD) was used to grow silicon dioxide pillars to electrically separate overhung aluminum electrodes from an aluminum ground plane. In addition to fabrication, we report techniques for modeling the control voltage solutions and the successful demonstration of trapping and shuttling ions in two identically constructed traps.
In this paper we present the design, modeling, and experimental testing of surface electrode ion traps fabricated in a heterostructure configuration comprising a silicon substrate, silicon dioxide insulators, and aluminum electrodes. This linear trap has a geometry with symmetric RF leads, two interior DC electrodes, and 40 individual lateral DC electrodes. Plasma enhanced chemical vapor deposition (PECVD) was used to grow silicon dioxide pillars to electrically separate overhung aluminum electrodes from an aluminum ground plane. In addition to fabrication, we report techniques for modeling the control voltage solutions and the successful demonstration of trapping and shuttling ions in two identically constructed traps.
An ion trap is a device to confine charged particles by utilizing electromagnetic fields.Since the trapped ions have a feasibility of the individual state manipulation, a long coherence time, and an ideal isolation from the surroundings, the ion-trap technology becomes one of the leading candidates for the physical implementation of quantum information processing.In order to build a large-scale integrated iontrap system for realizing complex quantum algorithms, microfabrication technologies have been applied to construct ion traps.The use of micro-electromechanical system (MEMS) ion-trap chip allows a scalable architecture of ion-trap arrays and integration of functional components to the trap chip, but a few side effects also arise.One of the most particular problems is stray fields generated by the charges accumulated on the sidewalls of thick dielectric pillars or the native oxide grown on metal surfaces, since the stray fields lead to ion micromotions which can cause heating and escape of the trapped ions.This dissertation presents a silicon surface ion-trap chip with dielectric sidewalls shielded by metal films.The oxide pillars supporting the top electrodes are fabricated to have overhang structures, and the upper and lower part of the pillars are coated by separate aluminum layers which are electrically isolated from each other.In order to evaluate the effects of the native ii metal oxide on the electrode surface to the charging phenomenon, a trap chip with an additional gold layer on the aluminum electrodes is also fabricated.An ultra-high vacuum (UHV) chamber, electrical connections, and an optical setup are prepared to trap 174 Yb + ions, and the ions are successfully trapped by using the experimental setup including the fabricated ion-trap chip.To evaluate the effectiveness of the proposed electrode structures, charging is intentionally induced on the chip surface by injecting a 355-nm pulse laser with 40-μW power perpendicularly to the chip surface.The intensity of the stray field is estimated by measuring the displacement of ion position after charging is induced.When the Al-based chips with exposed and Al-coated dielectric sidewalls are used, the standard deviation of the intensities of stray fields are 3.53, and 5.63 V/m, respectively.However, the standard deviation of the intensity of stray fields in the case of using Au-coated chip is 1.56 V/m, and any stray field is measured when the laser was injected on the surface or sidewalls of the gold-coated electrodes.These experimental results indicate that the gold coating on the surface of the aluminum electrodes and the sidewalls of dielectric pillars is effective for eliminating the generation of stray fields induced by static charges.
Trapped ions in Paul traps (radio frequency ion traps) are a promising candidate for the realization of a quantum computer. To date, experimental demonstrations of quantum computing and information processing with trapped ions have been limited to small numbers of quantum bits (qubits). The most prominent challenge to realise ion-trap quantum computation is to scale the system and control a large number of trapped ions coherently. Surface-electrode ion trap designs which are amenable to various microfabrication techniques offer a path to achieve this. In this work, design, fabrication and key operations of two types of surface-electrode ion traps, i.e. a Y-junction trap and a two-dimensional (2D) hexagonal lattice trap developed towards scaling ion-trap architectures, are presented. The steps involved in the fabrication of the ion-trap devices included photolithography, wet etch (hydrofluoric acid etch) and dry etch (deep reactive ion and inductively coupled plasma etching), and metal evaporation. The devices were fabricated on SOI substrates with different buried oxide thicknesses (i.e. 5 µm and 10 µm) and different metals for the trap electrodes (i.e. gold and aluminium). An extremely high-breakdown voltage up to 1 kV was measured in vacuum for the SOI-built test devices with a 10 µm-thick buried oxide formed by oxide film-to-oxide film bonding process. This is attributed to the deep V-shaped undercut profile of the buried oxide layer which resulted in a large breakdown path length, and so mitigating surface breakdown effects. Owing to the V-shaped undercut profile, the surface breakdown voltage was improved by 15% for the devices fabricated on SOI substrates with a 10 µm-thick buried oxide. In the first experiment, the demonstration of ytterbium (174Yb+) ion trapping in the 2D hexagonal lattice trap is achieved with a relatively long lifetime of a laser-cooled ion up to 90 minutes and ≤ 5 minutes without cooling in ultra-high vacuum system. The 2D lattice trap design allows for reliable trapping of 2D ion lattices, rudimentary shuttling between lattice sites and deterministic introducing of defects into the ion lattice. Based on all these abilities, such a 2D lattice trap with the predicted reduction of lattice spacing down to 32 µm can be configured as a versatile architecture for 2D quantum simulations with trapped ions. In the second experiment, microparticle trapping in the 2D lattice trap, performed in air, is achieved with the longest trapping lifetime of 60 minutes. Both gold and aluminium-coated electrodes also lead to comparable trapping performances. Furthermore, the in situ levitation of microparticles is successfully demonstrated at the maximum levitation height of 30 µm. This ability provides additional control on the trapping height which increases the overall functionality of the 2D lattice trap.
This paper presents a new microfabrication method for surface ion traps and experimental results with trapped ions. Fabricating ion trap chips is a very formidable task because the top electrodes are vertically spaced more than 10 µm from the bottom electrodes with an indented dielectric layer in the middle. Previous ion traps were fabricated using TEOS timed etch or tungsten sacrificial etch techniques. This paper presents a new microfabrication method, using copper as a sacrificial material for an aluminum-oxide-aluminum ion trap structure. Using the developed method the overhang dimensions of the top aluminum electrodes can be accurately controlled. Fabricated ion trap chips are installed in a 1 × 10−11Torr vacuum environment for ion trapping experiments. Successful results in trapping strings of171Yb+and174Yb+ions as well as manipulating171Yb+ions for qubit operation are demonstrated.
Further miniaturization of surface electrode ion trap is restricted by wire bonding connection. To resolve this restriction, integration of conventional surface electrode ion trap with through silicon via (TSV) interconnects is proposed and preliminarily demonstrated. Located directly underneath the DC and RF electrodes, TSVs can transmit the electrical signal from interposer to the electrodes on the top. In this work, electrostatic simulation and fabrication processes are introduced to justify the feasibility of this integration. From the electrical characterization (I-V and C-V tests) results, TSV-integrated ion trap exhibits smaller leakage current and lower capacitance than its wire bonding counterparts due to the elimination of large surface area.
Recent advances in quantum information processing with trapped ions have demonstrated the need for new ion trap architectures capable of holding and manipulating chains of many (>10) ions. Here we present the design and detailed characterization of a new linear trap, microfabricated with scalable complementary metal-oxide-semiconductor (CMOS) techniques, that is well-suited to this challenge. Forty-four individually controlled dc electrodes provide the many degrees of freedom required to construct anharmonic potential wells, shuttle ions, merge and split ion chains, precisely tune secular mode frequencies, and adjust the orientation of trap axes. Microfabricated capacitors on dc electrodes suppress radio-frequency pickup and excess micromotion, while a top-level ground layer simplifies modeling of electric fields and protects trap structures underneath. A localized aperture in the substrate provides access to the trapping region from an oven below, permitting deterministic loading of particular isotopic/elemental sequences via species-selective photoionization. The shapes of the aperture and radio-frequency electrodes are optimized to minimize perturbation of the trapping pseudopotential. Laboratory experiments verify simulated potentials and characterize trapping lifetimes, stray electric fields, and ion heating rates, while measurement and cancellation of spatially-varying stray electric fields permits the formation of nearly-equally spaced ion chains.
Surface electrode ion trap is a promising candidate for quantum information processing (QIP), due to its feasibilities towards large-scale fabrication and on-chip electro-optical integration. In this paper, surface electrode ion traps on different substrates (e.g., high-resistivity silicon, silicon with ground plane and glass) are fabricated, assembled and tested. To simultaneously leverage the established fabrication technique of silicon and superior insulation property of glass, we further demonstrate a novel ion trap design with heterogenous integration of silicon and glass, acting respectively as ion trap and interposer substrates. The vertical connection between the silicon ion trap and the glass interposer is achieved by through silicon via (TSV) and micro bump. This silicon-glass integrated system advances the development of ion trap and enriches the toolbox of scalable QIP.