Demonstration of a scalable, multiplexed ion trap for quantum information processing
David R. Leibrandt, Jaroslaw Labaziewicz, Robert Clark, Isaac L. Chuang, R. J. Epstein, C. Ospelkaus, Janus H. Wesenberg, J. J. Bollinger, Dietrich G. Leibfried, David J. Wineland, Daniel Stick, Jonathan David Sterk, Christopher R. Monroe, Pai, C. -S., Y.L. Low, Robert E. Frahm, Richard E. Slusher
A scalable, multiplexed ion trap for quantum information processing is fabricated and tested. The trap design and fabrication process are optimized for scalability to small trap size and large numbers of interconnected traps, and for integration of control electronics and optics. Multiple traps with similar designs are tested with Cd+, Mg+, and Sr+ ions at room temperature and with Sr+ at 6 K, with respective ion lifetimes of 90 s, 300 +/- 30 s, 56 +/- 6 s, and 4.5 +/- 1.1 hours. The motional heating rate for Mg+ at room temperature and a trap frequency of 1.6 MHz is measured to be 7 +/- 3 quanta per millisecond. For Sr+ at 6 K and 540 kHz the heating rate is measured to be 220 +/- 30 quanta per second.
A scalable, multiplexed ion trap for quantum information processing is fabricated and tested. The trap design and fabrication process are optimized for scalability to small trap size and large numbers of interconnected traps, and for integration of control electronics and optics. Multiple traps with similar designs are tested with Cd+, Mg+, and Sr+ ions at room temperature and with Sr+ at 6 K, with respective ion lifetimes of 90 s, 300 +/- 30 s, 56 +/- 6 s, and 4.5 +/- 1.1 hours. The motional heating rate for Mg+ at room temperature and a trap frequency of 1.6 MHz is measured to be 7 +/- 3 quanta per millisecond. For Sr+ at 6 K and 540 kHz the heating rate is measured to be 220 +/- 30 quanta per second.
A scalable, multiplexed ion trap for quantum information processing is fabricated and tested. The trap design and fabrication process are optimized for scalability to small trap size and large numbers of interconnected traps, and for integration of control electronics and optics. Multiple traps with similar designs are tested with 111Cd+, 25Mg+, and 88Sr+ ions at room temperature and with 88Sr+ at 6 K, with respective ion lifetimes of 90 s, 300 ± 30 s, 56 ± 6 s, and 4.5 ± 1.1 hours. The motional heating rate for 25Mg+ at room temperature and a trap frequency of 1.6 MHz is measured to be 7 ± 3 quanta per millisecond. For 88Sr+ at 6 K and 540 kHz the heating rate is measured to be 220 ± 30 quanta per second.
A fault-tolerant quantum computer is expected to require thousands of qubits. Trapped ion architectures provide a modular approach where the quantum register is divided into multiple subregisters connected by physically moving the corresponding ions. Transporting ions at scale comes with several challenges such as the need to connect thousands of control lines to an ion trap chip. Multiplexing the required control voltages from few input signals to multiple electrodes offers a solution to this wiring challenge. Here we demonstrate a quantum processing unit that combines a surface ion trap with a time multiplexer via a sample-and-hold technique that initially charges electrodes to fixed voltages and disconnects them during qubit operations. We characterize the unit's performance by measuring motional heating rates below one phonon per second in both open and closed switch configurations. We further characterize the sample and hold process and find that sampling intervals below 50 ms are sufficient to keep expected gate errors from decaying charges during the hold phase below 10−4. Our results indicate that the multiplexing scheme is compatible with high-fidelity operations.
Individual laser-cooled 24Mg+ ions are confined in a linear Paul trap with a novel geometry where gold electrodes are located in a single plane and the ions are trapped 40 microm above this plane. The relatively simple trap design and fabrication procedure are important for large-scale quantum information processing (QIP) using ions. Measured ion motional frequencies are compared to simulations. Measurements of ion recooling after cooling is temporarily suspended yield a heating rate of approximately 5 motional quanta per millisecond for a trap frequency of 2.83 MHz, sufficiently low to be useful for QIP.
With all the key elements of quantum computing in ion traps demonstrated by the research community, the focus is now placed on building more sophisticated traps with larger numbers of ions to allow practical scale information processing. One promising avenue is to store ions in and shuttle them between many independent traps which serve as potential interaction sites. The core of the work described in this thesis is the experimental evaluation of a microfabricated segmented ion trap, built by Sandia National Laboratories ("Sandia trap"). These experiments required construction of a wholly new optical setup including laser and detection systems, a vacuum system and control electronics. Among our experimental achievements were: successful loading of single and pairs of ions in the microscale trap, measurement of ion storage lifetime, measurement of the motional heating rate with a time-resolved Doppler-cooling method — which showed above than average heating, and implemented a single-ion shuttling method — which reliably transferred the ion through a distance of 360 μm (two DC electrode widths away) and back. These results have been used to improve the next version of the Sandia trap design. We also used computer modelling to study several aspects of ion traps: a mesoscopic ion trap designed for fast ion separation, simulated ion loading to quantify requirements for successful trapping in small and shallow traps, and analyzed a precise shuttling method — where the time dependence of the trapping potential is engineered such that there is minimal motional heating. The results show that ion trap arrays at the 100 μm distance scale are feasible and suggests that such multiple trap designs merit further study.
The electromagnetic manipulation of isolated ions has led to many advances in atomic physics, from laser cooling to precision metrology and quantum control. As technical capability in this area has grown, so has interest in building miniature electromagnetic traps for the development of large-scale quantum information processors. This thesis will primarily focus on using microfabrication techniques to build arrays of miniature ion traps, similar to techniques used in fabricating high component density microprocessors. A specific focus will be on research using a gallium arsenide/aluminum gallium arsenide heterostructure as a trap architecture, as well as the recent testing of different ion traps fabricated at outside foundries. The construction and characterization of a conventional ceramic trap capable of shuttling an ion through a junction will also be detailed, and reveal the need for moving towards lithographically fabricated traps. Combined, these serve as a set of proof-of-principle experiments pointing to methods for designing and building large scale arrays of ion traps capable of constituting a quantum information processor. As traps become smaller, electrical potentials on the electrodes have greater influence on the ion. This not only pertains to intentionally applied voltages, but also to deleterious noise sources, such as thermal Johnson noise and the more significant ``patch potential" noise, which both cause motional heating of the ion. These problematic noise sources dovetail with my thesis research into trap miniaturization since their effects become more pronounced and impossible to ignore for small trap sizes. Therefore characterizing them and investigating ways to suppress them have become an important component of my research. I will describe an experiment using a pair of movable needle electrodes to measure the ion heating rate corresponding to the harmonic frequency of the trap, the ion-electrode distance, and the electrode temperature. This information is used for characterizing the fluctuating potentials and exploring the possibility of suppressing motional heating by cooling the trap electrodes. This source of noise is also observed in other systems, and its characterization could potentially improve other precision experiments, such as those measuring deviations in the gravitational inverse square law with proximate masses.
Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. In such context, this thesis is committed to boost the scalability of ion trap by integrating advanced 3D interconnects (e.g., through silicon via) and other functional modules (e.g., silicon photonics and multilayer metallization). 3D interconnects are integrated in the half space underneath surface electrode, to replace conventional wire bonding that extends out of the surface. Silicon photonics (grating coupler and waveguide) in place of bulk optics and lenses are used for on-chip light routing and emission. Multilayer metallization is used to maintain the overall RF performance and enable high-density interconnection where necessary. Firstly, surface electrode ion traps on different substrates (namely high resistivity silicon, silicon with grounding plane and glass) are designed and fabricated. Standard CMOS back-end-of-line fabrication process on 12-inch wafer platform is employed. The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. Due to the incorporation of TSV, the original wire bonding pads as well as the connection circuits on the surface electrodes can be eliminated. As a result, the form factor of TSV integrated trap is reduced by ~10 times. Correspondingly, the parasitic capacitance between neighboring electrodes is reduced from >24 pF to 3 pF. Similarly, the insertion loss of TSV integrated trap drops to 0.11 dB, in sharp comparison to the previous traps on silicon substrates (up to 2.4 dB). Analytical models are built to respectively characterize the electrode capacitance and overall power loss, and a good agreement is achieved between the model and the measurement result. In addition, since TSV is located in the half space underneath the surface electrodes, the electrodes geometry design is enabled with high flexibility. Meanwhile, the laser obstruction issue due to the stick-out bonding wires has been resolved. In terms of the ion trapping performance, both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and the lifetime (~30 minutes) of TSV trap are comparable with non-cryogenic traps of similar dimensions. Moreover, a customized CPGA with patterned redistribution layer is used to locate TSV integrated trap directly in the absence of glass interposer, facilitating high-efficiency thermal management and upgrading the packaging flexibility. At the next stage, the co-integration of other functional modules such as silicon photonics and multilayer metallization with TSV trap is investigated. In silicon photonics module, waveguide and grating coupler are on-chip introduced in place of bulk optics to achieve localized light routing and emission. In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. The deviation between the simulation and measurement is largely due to the fabrication imperfection and the resultant sloped grating coupler profile. This thesis focuses on the scalability enhancement of ion trap by integrating TSV, silicon photonics and multilayer metallization into conventional ion trap. The results are promising and pave the way for the future large scale quantum computing based on trapped ion.