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arXiv:2605.16010

Demonstration of a Multiplexing Trapped Ion Quantum Processing Unit

F. Anmasser, M. Abu Zahra, K. Schüppert, M. Pototschnig, J. Wahl, M. Dietl, M. Pfeifer, Y. Colombe, J. Repp, M. Brandl, P. Schindler, C. Rössler

quant-phSubmitted May 15, 2026• Announced May 18, 2026• 0 citations
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Abstract

A fault-tolerant quantum computer is expected to require thousands of qubits. Trapped ion architectures provide a modular approach where the quantum register is divided into multiple subregisters connected by physically moving the corresponding ions. Transporting ions at scale comes with several challenges such as the need to connect thousands of control lines to an ion trap chip. Multiplexing the required control voltages from few input signals to multiple electrodes offers a solution to this wiring challenge. Here we demonstrate a quantum processing unit that combines a surface ion trap with a time multiplexer via a sample-and-hold technique that initially charges electrodes to fixed voltages and disconnects them during qubit operations. We characterize the unit's performance by measuring motional heating rates below one phonon per second in both open and closed switch configurations. We further characterize the sample and hold process and find that sampling intervals below 50 ms are sufficient to keep expected gate errors from decaying charges during the hold phase below $10^{-4}$. Our results indicate that the multiplexing scheme is compatible with high-fidelity operations.

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Jonathan David Sterk, Matthew G. Blain, Delaney, M. +11 more

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arXiv:2403.00208•Mar 1, 2024•1 citation
A fault-tolerant quantum computer is expected to require thousands of qubits. Trapped ion architectures provide a modular approach where the quantum register is divided into multiple subregisters connected by physically moving the corresponding ions. Transporting ions at scale comes with several challenges such as the need to connect thousands of control lines to an ion trap chip. Multiplexing the required control voltages from few input signals to multiple electrodes offers a solution to this wiring challenge. Here we demonstrate a quantum processing unit that combines a surface ion trap with a time multiplexer via a sample-and-hold technique that initially charges electrodes to fixed voltages and disconnects them during qubit operations. We characterize the unit's performance by measuring motional heating rates below one phonon per second in both open and closed switch configurations. We further characterize the sample and hold process and find that sampling intervals below 50 ms are sufficient to keep expected gate errors from decaying charges during the hold phase below 10−410^{-4}10−4. Our results indicate that the multiplexing scheme is compatible with high-fidelity operations.
The trapped-ion QCCD (quantum charge-coupled device) architecture proposal lays out a blueprint for a universal quantum computer. The design begins with electrodes patterned on a two-dimensional surface configured to trap multiple arrays of ions (or ion crystals). Communication within the ion crystal network allows for the machine to be scaled while keeping the number of ions in each crystal to a small number, thereby preserving the low error rates demonstrated in trapped-ion experiments. By proposing to communicate quantum information by moving the ions through space to interact with other distant ions, the architecture creates a quantum computer endowed with full-connectivity. However, engineering this fully-connected computer introduces a host of difficulties that have precluded the architecture from being fully realized in the twenty years since its proposal. Using a Honeywell cryogenic surface trap, we report on the integration of all necessary ingredients of the QCCD architecture into a programmable trapped-ion quantum computer. Using four and six qubit circuits, the system level performance of the processor is quantified by the fidelity of a teleported CNOT gate utilizing mid-circuit measurement and a quantum volume measurement of 26=642^6=6426=64. By demonstrating that the low error rates achievable in small ion crystals can be successfully integrated with a scalable trap design, parallel optical delivery, and fast ion transport, the QCCD architecture is shown to be a viable path toward large quantum computers. Atomic ions provide perfectly identical, high-fidelity qubits. Our work shows that the QCCD architecture built around these qubits will provide high performance quantum computers, likely enabling important near-term demonstrations such as quantum error correction and quantum advantage.
The trapped atomic ion qubits feature desirable properties for use in a quantum computer such as long coherence times, high qubit readout fidelity, and universal logic gates. While these essential properties have been demonstrated, the ability to scale a trapped ion quantum system has not yet been shown. The challenge of scaling the system calls for methods to realize high-fidelity logic gates in scalable trap structures. Surface electrode ion traps, that are microfabricated from a silicon substrate, provide a scalable platform for trapping ion qubits only if high-fidelity operations are achievable in these structures. Here, we present a system for trapping and manipulating ions in a scalable surface trap. Trapping times exceeding 20 minutes without laser cooling, and heating rates as low as 0.8 quanta/ms indicate stable trapping conditions in these microtraps. Coherence times of more than one second verify adequate qubit and control field stability. We demonstrate low-error single-qubit gates performed using stimulated Raman transitions driven by lasers that are tightly focused on the ion qubit. Digital feedback loops are implemented to control the driving field's amplitude and frequency. Gate errors are measured using a randomized benchmarking protocol for single qubit gates, where residual amplitude error in the control beam is compensated using various pulse sequence techniques. Using pulse compensation, we demonstrate single qubit gates with an average error per randomized Clifford group gate of 3.6(3)times10−43.6(3)\\times10^{-4}3.6(3)times10−4, which is below the fault-tolerant threshold for some error-correction schemes.
The scaling up of trapped-ion quantum processors based on the quantum charge-coupled device (QCCD) architecture is difficult owing to the extensive electronics and high-density wiring required to control numerous trap electrodes. In conventional QCCD architectures, each trap electrode is controlled via a dedicated digital-to-analog converter (DAC). The conventional approach places an overwhelming demand on electronic resources and wiring complexity. This is because the number of trap electrodes typically exceeds the number of trapped-ion qubits. This study proposes a method that leverages a high-speed DAC to generate time-division multiplexed signals to control a large-scale QCCD trapped-ion quantum processor. The proposed method replaces conventional DACs with a single high-speed DAC that generates the complete voltage waveforms required to control the trap electrodes, thereby significantly reducing the wiring complexity and overall resource requirements. Based on realistic parameters and commercially available electronics, our analysis demonstrates that a QCCD trapped-ion quantum computer with10,000\mathbf{1 0, 0 0 0}10,000trap electrodes can be controlled using only 13 field-programmable gate arrays and 104 high-speed DACs. This is in stark contrast to the10,000\mathbf{1 0, 0 0 0}10,000dedicated DACs required by conventional control methods. Consequently, employing this approach, we developed a proof-of-concept electronic system and evaluated its analog output performance.
One of the most formidable challenges of scaling up quantum computers is that of control-signal delivery.Today's small-scale quantum computers typically connect each qubit to one or more separate external signal sources.This approach is not scalable due to the input/output (I/O) limitations of the qubit chip, necessitating the integration of control electronics.However, it is no small feat to shrink control electronics into a small package that is compatible with qubit-chip fabrication and operational constraints without sacrificing performance.This so-called "wiring challenge" is likely to impact the development of more powerful quantum computers even in the near term.In this paper, we address the wiring challenge of trapped-ion quantum computers.We describe a control architecture called WISE (Wiring using Integrated Switching Electronics), which significantly reduces the I/O requirements of ion-trap quantum computing chips without compromising performance.Our method relies on judiciously integrating simple switching electronics into the ion-trap chip-in a way that is compatible with its fabrication and operation constraints-while the complex electronics remain external.To demonstrate its power, we describe how the WISE architecture can be used to operate a fully connected 1000-qubit trapped-ion quantum computer using approximately 200 signal sources at a speed of approximately 40-2600 quantum gate layers per second.
Trapped-ion Quantum Charge-Coupled Devices (QCCD) are a leading contender for quantum computing, but their scalability is constrained by control wiring and electronics. Wiring using Integrated Switching Electronics (WISE), a recently proposed QCCD architecture, reduces wiring through multiplexing and integrated switching hardware. However, this leaves an execution model with limited parallelism and limited flexibility in ion movement. Further, these devices need to be paired with a quantum error correction (QEC) code to enable fault-tolerant quantum computation (FTQC). Can WISE architectures efficiently support FTQC requirements? Which QEC choices, device and control parameters are practical? We present WISER, a cross-layer design-space exploration framework for trapped-ion systems with multiplexed control. WISER combines a WISE-specific SAT-based compiler, a physics-informed noise model and logical-memory simulation to estimate logical error rates, logical clock speeds and control power across hardware parameters and QEC families. Its compiler reduces routing time by 2.62.62.6--18.8×18.8\times18.8× relative to a greedy WISE-compatible baseline. Our analysis provides concrete design guidance. Two-ion traps with 161616-way multiplexing, 8×8\times8× lower than the original WISE proposal, give the fastest logical clock that meets our reliability and cold-stage power targets. With current hardware parameters, the distance-7 surface code is the only evaluated code to meet our early-FTQC screen, at 4.58 4.58\,4.58Hz and 2.04 2.04\,2.04W of DAC power per logical qubit. At this operating point, ion transport and recooling take 949494--96%96\%96% of the WISE cycle, and even without them sample-and-hold electrode charging leaves millisecond-scale syndrome-extraction rounds.
Surface ion traps with two-dimensional layouts of trapping regions are natural architectures for storing large numbers of ions and supporting the connectivity needed to implement quantum algorithms. Many of the components and operations needed to fully exploit this architecture have already been demonstrated, including operation at cryogenic temperatures with low heating, low excitation transport, and ion control and detection with integrated photonics. Here we demonstrate a trap that addresses the scaling challenge of increasing power dissipation as the RF electrode increases in size. By raising the RF electrode and removing most of the insulating dielectric layer below it we reduce both ohmic and dielectric power dissipation. We also measure heating rates across a range of motional frequencies and for different voltage sources in a trap with a raised RF electrode but solid dielectric.