Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

arXiv:2609.13546

WISER: Systematic Design-Space Exploration of Trapped Ions with Multiplexed Control

Scott Jones, Song-qing-hao Yang, Prakash Murali

quant-phcs.ARSubmitted Sep 11, 2026• Announced Sep 15, 2026• 0 citations• Revised Oct 2, 2026 (v2)
v1 · Sep 11, 2026v2 · Oct 2, 2026
arXivHTMLPDF

Abstract

Trapped-ion Quantum Charge-Coupled Devices (QCCD) are a leading contender for quantum computing, but their scalability is constrained by control wiring and electronics. Wiring using Integrated Switching Electronics (WISE), a recently proposed QCCD architecture, reduces wiring through multiplexing and integrated switching hardware. However, this leaves an execution model with limited parallelism and limited flexibility in ion movement. Further, these devices need to be paired with a quantum error correction (QEC) code to enable fault-tolerant quantum computation (FTQC). Can WISE architectures efficiently support FTQC requirements? Which QEC choices, device and control parameters are practical? We present WISER, a cross-layer design-space exploration framework for trapped-ion systems with multiplexed control. WISER combines a WISE-specific SAT-based compiler, a physics-informed noise model and logical-memory simulation to estimate logical error rates, logical clock speeds and control power across hardware parameters and QEC families. Its compiler reduces routing time by $2.6$--$18.8\times$ relative to a greedy WISE-compatible baseline. Our analysis provides concrete design guidance. Two-ion traps with $16$-way multiplexing, $8\times$ lower than the original WISE proposal, give the fastest logical clock that meets our reliability and cold-stage power targets. With current hardware parameters, the distance-7 surface code is the only evaluated code to meet our early-FTQC screen, at $4.58\,$Hz and $2.04\,$W of DAC power per logical qubit. At this operating point, ion transport and recooling take $94$--$96\%$ of the WISE cycle, and even without them sample-and-hold electrode charging leaves millisecond-scale syndrome-extraction rounds.

Comments
Version 2, 31 pages, 12 figures, 5 tables

Related papers

Architecting Scalable Trapped Ion Quantum Computers using Surface Codes

Scott Jones, Prakash Murali

Trapped ion (TI) qubits are a leading quantum computing platform. Current TI systems have less than 60 qubits, but a modular architecture known as the Quantum Charge-Coupled Device (QCCD) is a promising path to scale up devices. There is a large gap between the error rates of near-term systems (10-3 to 10-4) and the requirements of practical applications (below 10-9). To bridge this gap, we require Quantum Error Correction (QEC) to build logical qubits that are composed of multiple physical qubits. While logical qubits have been demonstrated on TI qubits, these demonstrations are restricted to small codes and systems. There is no clarity on how QCCD systems should be designed to implement practical-scale QEC. This paper studies how surface codes, a standard QEC scheme, can be implemented efficiently on QCCD-based systems. To examine how architectural parameters of a QCCD system can be tuned for surface codes, we develop a near-optimal topology-aware compilation method that outperforms existing QCCD compilers by an average of 3.8X in terms of logical clock speed. We use this compiler to examine how hardware trap capacity, connectivity and electrode wiring choices can be optimised for surface code implementation. In particular, we demonstrate that small traps of two ions are surprisingly ideal from both a performance-optimal and hardware-efficiency standpoint. This result runs counter to prior intuition that larger traps (20-30 ions) would be preferable, and has the potential to inform design choices for upcoming systems.

arXiv:2510.23519•International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)•Mar 10, 2026•0 citations

Multiplexed Control at Scale for Electrode Arrays in Trapped-Ion Quantum Processors

Ryutaro Ohira, Shinichi Morisaka, Ippei Nakamura +2 more

The scaling up of trapped-ion quantum processors based on the quantum charge-coupled device (QCCD) architecture is difficult owing to the extensive electronics and high-density wiring required to control numerous trap electrodes. In conventional QCCD architectures, each trap electrode is controlled via a dedicated digital-to-analog converter (DAC). The conventional approach places an overwhelming demand on electronic resources and wiring complexity. This is because the number of trap electrodes typically exceeds the number of trapped-ion qubits. This study proposes a method that leverages a high-speed DAC to generate time-division multiplexed signals to control a large-scale QCCD trapped-ion quantum processor. The proposed method replaces conventional DACs with a single high-speed DAC that generates the complete voltage waveforms required to control the trap electrodes, thereby significantly reducing the wiring complexity and overall resource requirements. Based on realistic parameters and commercially available electronics, our analysis demonstrates that a QCCD trapped-ion quantum computer with$\mathbf{1 0, 0 0 0}$trap electrodes can be controlled using only 13 field-programmable gate arrays and 104 high-speed DACs. This is in stark contrast to the$\mathbf{1 0, 0 0 0}$dedicated DACs required by conventional control methods. Consequently, employing this approach, we developed a proof-of-concept electronic system and evaluated its analog output performance.

IEEE International Conference on Quantum Computing and Engineering (QCE)•Aug 30, 2025•1 citation

Demonstration of a Multiplexing Trapped Ion Quantum Processing Unit

F. Anmasser, M. Abu Zahra, K. Schüppert +9 more

A fault-tolerant quantum computer is expected to require thousands of qubits. Trapped ion architectures provide a modular approach where the quantum register is divided into multiple subregisters connected by physically moving the corresponding ions. Transporting ions at scale comes with several challenges such as the need to connect thousands of control lines to an ion trap chip. Multiplexing the required control voltages from few input signals to multiple electrodes offers a solution to this wiring challenge. Here we demonstrate a quantum processing unit that combines a surface ion trap with a time multiplexer via a sample-and-hold technique that initially charges electrodes to fixed voltages and disconnects them during qubit operations. We characterize the unit's performance by measuring motional heating rates below one phonon per second in both open and closed switch configurations. We further characterize the sample and hold process and find that sampling intervals below 50 ms are sufficient to keep expected gate errors from decaying charges during the hold phase below $10^{-4}$. Our results indicate that the multiplexing scheme is compatible with high-fidelity operations.

quant-pharXiv:2605.16010•May 18, 2026•0 citations

Quantum Compiler Design for Fault-Tolerant Quantum Computing

Chenghong Zhu, Jiahan Chen, Keming He +9 more

Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding. This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.

quant-pharXiv:2609.17465•Sep 16, 2026•0 citations

How to Wire a 1000 -Qubit Trapped-Ion Quantum Computer

Maciej Malinowski, D. T. C. Allcock, Christopher J. Ballance

One of the most formidable challenges of scaling up quantum computers is that of control-signal delivery.Today's small-scale quantum computers typically connect each qubit to one or more separate external signal sources.This approach is not scalable due to the input/output (I/O) limitations of the qubit chip, necessitating the integration of control electronics.However, it is no small feat to shrink control electronics into a small package that is compatible with qubit-chip fabrication and operational constraints without sacrificing performance.This so-called "wiring challenge" is likely to impact the development of more powerful quantum computers even in the near term.In this paper, we address the wiring challenge of trapped-ion quantum computers.We describe a control architecture called WISE (Wiring using Integrated Switching Electronics), which significantly reduces the I/O requirements of ion-trap quantum computing chips without compromising performance.Our method relies on judiciously integrating simple switching electronics into the ion-trap chip-in a way that is compatible with its fabrication and operation constraints-while the complex electronics remain external.To demonstrate its power, we describe how the WISE architecture can be used to operate a fully connected 1000-qubit trapped-ion quantum computer using approximately 200 signal sources at a speed of approximately 40-2600 quantum gate layers per second.

arXiv:2305.12773•PRX Quantum•Oct 19, 2023•54 citations

Architecting Noisy Intermediate-Scale Trapped Ion Quantum Computers

Prakash Murali, Dripto M. Debroy, Kenneth R. Brown +1 more

Trapped ions (TI) are a leading candidate for building Noisy Intermediate-Scale Quantum (NISQ) hardware. TI qubits have fundamental advantages over other technologies such as superconducting qubits, including high qubit quality, coherence and connectivity. However, current TI systems are small in size, with 5-20 qubits and typically use a single trap architecture which has fundamental scalability limitations. To progress towards the next major milestone of 50-100 qubit TI devices, a modular architecture termed the Quantum Charge Coupled Device (QCCD) has been proposed. In a QCCD-based TI device, small traps are connected through ion shuttling. While the basic hardware components for such devices have been demonstrated, building a 50-100 qubit system is challenging because of a wide range of design possibilities for trap sizing, communication topology and gate implementations and the need to match diverse application resource requirements.Towards realizing QCCD-based TI systems with 50-100 qubits, we perform an extensive application-driven architectural study evaluating the key design choices of trap sizing, communication topology and operation implementation methods. To enable our study, we built a design toolflow which takes a QCCD architecture's parameters as input, along with a set of applications and realistic hardware performance models. Our toolflow maps the applications onto the target device and simulates their execution to compute metrics such as application run time, reliability and device noise rates. Using six applications and several hardware design points, we show that trap sizing and communication topology choices can impact application reliability by up to three orders of magnitude. Microarchitectural gate implementation choices influence reliability by another order of magnitude. From these studies, we provide concrete recommendations to tune these choices to achieve highly reliable and performant application executions. With industry and academic efforts underway to build TI devices with 50-100 qubits, our insights have the potential to influence QC hardware in the near-future and accelerate the progress towards practical QC systems.

arXiv:2004.04706•Proceedings - International Symposium on Computer Architecture/Proceedings•May 1, 2020•83 citations
Trapped-ion Quantum Charge-Coupled Devices (QCCD) are a leading contender for quantum computing, but their scalability is constrained by control wiring and electronics. Wiring using Integrated Switching Electronics (WISE), a recently proposed QCCD architecture, reduces wiring through multiplexing and integrated switching hardware. However, this leaves an execution model with limited parallelism and limited flexibility in ion movement. Further, these devices need to be paired with a quantum error correction (QEC) code to enable fault-tolerant quantum computation (FTQC). Can WISE architectures efficiently support FTQC requirements? Which QEC choices, device and control parameters are practical?
We present WISER, a cross-layer design-space exploration framework for trapped-ion systems with multiplexed control. WISER combines a WISE-specific SAT-based compiler, a physics-informed noise model and logical-memory simulation to estimate logical error rates, logical clock speeds and control power across hardware parameters and QEC families. Its compiler reduces routing time by 2.62.62.6--18.8×18.8\times18.8× relative to a greedy WISE-compatible baseline.
Our analysis provides concrete design guidance. Two-ion traps with 161616-way multiplexing, 8×8\times8× lower than the original WISE proposal, give the fastest logical clock that meets our reliability and cold-stage power targets. With current hardware parameters, the distance-7 surface code is the only evaluated code to meet our early-FTQC screen, at 4.58 4.58\,4.58Hz and 2.04 2.04\,2.04W of DAC power per logical qubit. At this operating point, ion transport and recooling take 949494--96%96\%96% of the WISE cycle, and even without them sample-and-hold electrode charging leaves millisecond-scale syndrome-extraction rounds.
Trapped ion (TI) qubits are a leading quantum computing platform. Current TI systems have less than 60 qubits, but a modular architecture known as the Quantum Charge-Coupled Device (QCCD) is a promising path to scale up devices. There is a large gap between the error rates of near-term systems (10-3 to 10-4) and the requirements of practical applications (below 10-9). To bridge this gap, we require Quantum Error Correction (QEC) to build logical qubits that are composed of multiple physical qubits. While logical qubits have been demonstrated on TI qubits, these demonstrations are restricted to small codes and systems. There is no clarity on how QCCD systems should be designed to implement practical-scale QEC. This paper studies how surface codes, a standard QEC scheme, can be implemented efficiently on QCCD-based systems. To examine how architectural parameters of a QCCD system can be tuned for surface codes, we develop a near-optimal topology-aware compilation method that outperforms existing QCCD compilers by an average of 3.8X in terms of logical clock speed. We use this compiler to examine how hardware trap capacity, connectivity and electrode wiring choices can be optimised for surface code implementation. In particular, we demonstrate that small traps of two ions are surprisingly ideal from both a performance-optimal and hardware-efficiency standpoint. This result runs counter to prior intuition that larger traps (20-30 ions) would be preferable, and has the potential to inform design choices for upcoming systems.
The scaling up of trapped-ion quantum processors based on the quantum charge-coupled device (QCCD) architecture is difficult owing to the extensive electronics and high-density wiring required to control numerous trap electrodes. In conventional QCCD architectures, each trap electrode is controlled via a dedicated digital-to-analog converter (DAC). The conventional approach places an overwhelming demand on electronic resources and wiring complexity. This is because the number of trap electrodes typically exceeds the number of trapped-ion qubits. This study proposes a method that leverages a high-speed DAC to generate time-division multiplexed signals to control a large-scale QCCD trapped-ion quantum processor. The proposed method replaces conventional DACs with a single high-speed DAC that generates the complete voltage waveforms required to control the trap electrodes, thereby significantly reducing the wiring complexity and overall resource requirements. Based on realistic parameters and commercially available electronics, our analysis demonstrates that a QCCD trapped-ion quantum computer with10,000\mathbf{1 0, 0 0 0}10,000trap electrodes can be controlled using only 13 field-programmable gate arrays and 104 high-speed DACs. This is in stark contrast to the10,000\mathbf{1 0, 0 0 0}10,000dedicated DACs required by conventional control methods. Consequently, employing this approach, we developed a proof-of-concept electronic system and evaluated its analog output performance.
A fault-tolerant quantum computer is expected to require thousands of qubits. Trapped ion architectures provide a modular approach where the quantum register is divided into multiple subregisters connected by physically moving the corresponding ions. Transporting ions at scale comes with several challenges such as the need to connect thousands of control lines to an ion trap chip. Multiplexing the required control voltages from few input signals to multiple electrodes offers a solution to this wiring challenge. Here we demonstrate a quantum processing unit that combines a surface ion trap with a time multiplexer via a sample-and-hold technique that initially charges electrodes to fixed voltages and disconnects them during qubit operations. We characterize the unit's performance by measuring motional heating rates below one phonon per second in both open and closed switch configurations. We further characterize the sample and hold process and find that sampling intervals below 50 ms are sufficient to keep expected gate errors from decaying charges during the hold phase below 10−410^{-4}10−4. Our results indicate that the multiplexing scheme is compatible with high-fidelity operations.
Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding. This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.
One of the most formidable challenges of scaling up quantum computers is that of control-signal delivery.Today's small-scale quantum computers typically connect each qubit to one or more separate external signal sources.This approach is not scalable due to the input/output (I/O) limitations of the qubit chip, necessitating the integration of control electronics.However, it is no small feat to shrink control electronics into a small package that is compatible with qubit-chip fabrication and operational constraints without sacrificing performance.This so-called "wiring challenge" is likely to impact the development of more powerful quantum computers even in the near term.In this paper, we address the wiring challenge of trapped-ion quantum computers.We describe a control architecture called WISE (Wiring using Integrated Switching Electronics), which significantly reduces the I/O requirements of ion-trap quantum computing chips without compromising performance.Our method relies on judiciously integrating simple switching electronics into the ion-trap chip-in a way that is compatible with its fabrication and operation constraints-while the complex electronics remain external.To demonstrate its power, we describe how the WISE architecture can be used to operate a fully connected 1000-qubit trapped-ion quantum computer using approximately 200 signal sources at a speed of approximately 40-2600 quantum gate layers per second.
Trapped ions (TI) are a leading candidate for building Noisy Intermediate-Scale Quantum (NISQ) hardware. TI qubits have fundamental advantages over other technologies such as superconducting qubits, including high qubit quality, coherence and connectivity. However, current TI systems are small in size, with 5-20 qubits and typically use a single trap architecture which has fundamental scalability limitations. To progress towards the next major milestone of 50-100 qubit TI devices, a modular architecture termed the Quantum Charge Coupled Device (QCCD) has been proposed. In a QCCD-based TI device, small traps are connected through ion shuttling. While the basic hardware components for such devices have been demonstrated, building a 50-100 qubit system is challenging because of a wide range of design possibilities for trap sizing, communication topology and gate implementations and the need to match diverse application resource requirements.Towards realizing QCCD-based TI systems with 50-100 qubits, we perform an extensive application-driven architectural study evaluating the key design choices of trap sizing, communication topology and operation implementation methods. To enable our study, we built a design toolflow which takes a QCCD architecture's parameters as input, along with a set of applications and realistic hardware performance models. Our toolflow maps the applications onto the target device and simulates their execution to compute metrics such as application run time, reliability and device noise rates. Using six applications and several hardware design points, we show that trap sizing and communication topology choices can impact application reliability by up to three orders of magnitude. Microarchitectural gate implementation choices influence reliability by another order of magnitude. From these studies, we provide concrete recommendations to tune these choices to achieve highly reliable and performant application executions. With industry and academic efforts underway to build TI devices with 50-100 qubits, our insights have the potential to influence QC hardware in the near-future and accelerate the progress towards practical QC systems.