The external control circuits of quantum gates inevitably introduce a small but finite noise to the operation of quantum computers. The complex modes of decoherence introduced by this noise are not covered by the common error models. Using the controlled-phase gate as an example, the effect of gate control noise on decoherence is investigated for different quantum computer architectures. It is shown that the decoherence rate rises faster than linearly with the length of a quantum register for most cases considered, adding to the challenge of implementing proposed error correcting and fault tolerant computation schemes. Sometimes an unwanted effective inter-qubit coupling associated with the noise appears.
The external control circuits of quantum gates inevitably introduce a small but finite noise to the operation of quantum computers. The complex modes of decoherence introduced by this noise are not covered by the common error models. Using the controlled-phase gate as an example, the effect of gate control noise on decoherence is investigated for different quantum computer architectures. It is shown that the decoherence rate rises faster than linearly with the length of a quantum register for most cases considered, adding to the challenge of implementing proposed error correcting and fault tolerant computation schemes. Sometimes an unwanted effective inter-qubit coupling associated with the noise appears.
Quantum computation has become a very active field ever since the discovery that quantum computers can be much more powerful than their classical counterparts. Decoherence of the qubits caused by the inevitable interaction with the noisy environment is the major obstacle to realization of quantum computation. A recent innovative discovery is that reliable quantum computation is possible provided that the error per operation caused by decoherence is below a threshold value. The estimated threshold error rate is about 10/sup -6/. With the present technology, the real noise seems necessarily beyond this threshold. Therefore, it is essentially important to further suppress noise before taking the procedure of fault-tolerant quantum error correction. We propose a noise suppression scheme which operates by applying a sequence of bit-flipping and phase-flipping pulses on the system, with the pulse period less than the noise correlation time.
One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016)PRLTAO0031-900710.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.
Abstract We study the effectiveness of quantum error correction against coherent noise. Coherent errors (for example, unitary noise) can interfere constructively, so that in some cases the average infidelity of a quantum circuit subjected to coherent errors may increase quadratically with the circuit size; in contrast, when errors are incoherent (for example, depolarizing noise), the average infidelity increases at worst linearly with circuit size. We consider the performance of quantum stabilizer codes against a noise model in which a unitary rotation is applied to each qubit, where the axes and angles of rotation are nearly the same for all qubits. In particular, we show that for the toric code subject to such independent coherent noise, and for minimal-weight decoding, the logical channel after error correction becomes increasingly incoherent as the length of the code increases, provided the noise strength decays inversely with the code distance. A similar conclusion holds for weakly correlated coherent noise. Our methods can also be used for analyzing the performance of other codes and fault-tolerant protocols against coherent noise. However, our result does not show that the coherence of the logical channel is suppressed in the more physically relevant case where the noise strength is held constant as the code block grows, and we recount the difficulties that prevented us from extending the result to that case. Nevertheless our work supports the idea that fault-tolerant quantum computing schemes will work effectively against coherent noise, providing encouraging news for quantum hardware builders who worry about the damaging effects of control errors and coherent interactions with the environment.
Quantum low-density parity check (qLDPC) codes are among the leading candidates to realize error-corrected quantum memories with low qubit overhead. Potentially high encoding rates and large distance relative to their block size make them appealing for practical suppression of noise in near-term quantum computers. In addition to increased qubit-connectivity requirements compared to more conventional topological quantum error correcting codes, qLDPC codes remain notoriously hard to compute with. In this work, we introduce a construction to implement all Clifford quantum gate operations on the recently introduced lift-connected surface (LCS) codes (Old et al. 2024). These codes can be implemented in a 3D-local architecture and achieve asymptotic scaling [[n,O(n1/3),O(n1/3)]]. In particular, LCS codes realize favorable instances with small numbers of qubits: For the [[15,3,3]] LCS code, we provide deterministic fault-tolerant (FT) circuits of the logical gate set {Hi,Hi,CiXj}i,j∈(0,1,2) based on flag qubits. By adding a procedure for FT magic state preparation, we show quantitatively how to realize an FT universal gate set in d=3 LCS codes. Numerical simulations indicate that our gate constructions can attain pseudothresholds in the range pth≈4.8⋅10−3−1.2⋅10−2 for circuit-level noise. The schemes use a moderate number of qubits and are therefore feasible for near-term experiments, facilitating progress for fault-tolerant error corrected logic in high-rate qLPDC codes.
This review synthesizes current understanding of decoherence pathways across leading hardware platforms and explains why several experimentally observed noise features—drift, burst events, coherent components, correlated and non-Markovian structure, and leakage—can be disproportionately damaging for QEC. Decoherence remains the dominant impediment to scalable quantum computing because it is not a single error mechanism but a system-level phenomenon arising from materials defects, electromagnetic loss, control electronics, measurement backaction, and the broader environment in which a processor operates. Quantum error correction (QEC) is designed to algorithmically suppress physical noise, yet its practical success depends on how closely real devices satisfy the assumptions under which fault tolerance is proved: approximate locality, weak temporal correlations, sufficiently stochastic error statistics, low leakage, and reliable syndrome extraction. We then evaluate fundamental and engineering challenges that shape the viability of QEC at scale: syndrome measurement fidelity, correlated error suppression, decoding latency and classical co-processing, architectural constraints (connectivity, crosstalk, calibration overhead), and the resource cost of implementing a universal fault-tolerant gate set. Recent demonstrations of below-threshold behaviour and “break-even” regimes show that QEC is transitioning from theory to practice, but also clarify what remains unresolved: maintaining stable noise below fault-tolerance targets over long times, scaling to many logical qubits with low correlated-error rates, and integrating hardware-aware codes and decoders. We conclude with research priorities that treat decoherence and QEC as part of a co-designed stack spanning device physics, control, architecture, and algorithms.
Decoherence of quantum states is a major hurdle towards scalable and reliable quantum computing. Lower decoherence (i.e., higher fidelity) can alleviate the error correction overhead and obviate the need for energy-intensive noise reduction techniques e.g., cryogenic cooling. In this paper, we performed a noise-induced decoherence analysis of single and multi-qubit quantum gates using physics-based simulations. The analysis indicates that (i) decoherence depends on the input state and the gate type. Larger number of ∣1⟩ states worsen the decoherence; (ii) amplitude damping is more detrimental than phase damping; (iii) shorter depth implementation of a quantum function can achieve lower decoherence. Simulations indicate 20\% improvement in the fidelity of a quantum adder when realized using lower depth topology. The insights developed in this paper can be exploited by the circuit designer to choose the right gates and logic implementation to optimize the system-level fidelity.