We analyze probabilistic realizations of programmable quantum processors that allow us to realize unitary operations on qubits as well as on qudits. Programmable processors are composed of two inputs — the data register and the program register. In the input state of the program register information about the operation that is supposed to be performed on the data is encoded. At the output of the probabilistic processor a measurement over the program register is performed. An intrinsic property of probabilistic processors is that they sometimes fail, but we know when this happens. We present a complete analysis of two processors: (1) The so-called [Formula: see text] processor that is based on a simple controlled-NOT gate. (2) The so-called [Formula: see text] processor that utilizes the quantum-information-distributor circuit.
We present a probabilistic quantum processor for qubits. The processor itself is represented by a fixed array of gates. The input of the processor is constituted by two registers. In the program register the set of instructions (program) is encoded. This program is applied to the data register. The processor we present can perform any operation on a single qubit with a certain probability. If the operation is unitary, the probability is in general 1/4, but for more restricted sets of operators the probability can be higher.
A universal programmable quantum processor uses program quantum states to apply an arbitrary quantum channel to an input state. We generalize the concept of a finite-dimensional programmable quantum processor to infinite dimensions assuming an energy constraint on the input and output of the target quantum channels. Upper and lower bounds for the required program dimension, to approximately implement energy-limited quantum channels, are provided. In particular, we consider the implementation of Gaussian channels. Due to their practical relevance, we investigate the resource requirements for gauge covariant Gaussian channels. Additionally, we give upper and lower bounds for the program dimension of a processor implementing all Gaussian unitary channels.
Similar to a classical processor, which is an algorithm for reading a program and executing its instructions on input data, a universal programmable quantum processor is a fixed quantum channel that reads a quantum program
∣ψU⟩ that causes the processor to approximately apply an arbitrary unitary
U to a quantum data register. The present work focuses on a class of simple programmable quantum processors for implementing reflection operators, i.e.
U=eiπ∣ψ⟩⟨ψ∣ for an arbitrary pure state
∣ψ⟩ of finite dimension
d. Unlike quantum programs that assume query access to
U, our program takes the form of independent copies of the state to be reflected about
∣ψU⟩=∣ψ⟩⊗n. We then identify the worst-case optimal algorithm among all processors of the form
trProgram[V(∣ϕ⟩⟨ϕ∣⊗(∣ψ⟩⟨ψ∣)⊗n)V†] where the algorithm
V is a unitary linear combination of permutations. By generalizing these algorithms to processors for arbitrary-angle rotations,
eiα∣ψ⟩⟨ψ∣ for
α∈R, we give a construction for a universal programmable processor with better scaling in
d. For programming reflections, we obtain a tight analytical lower bound on the program dimension by bounding the Holevo information of an ensemble of reflections applied to an entangled probe state. The lower bound makes use of a block decomposition of the uniform ensemble of reflected states with respect to irreps of the partially transposed permutation matrix algebra, and two representation-theoretic conjectures based on extensive numerical evidence.
A quantum processor is a device with a data register and a program register. The input to the program register determines the operation, which is a completely positive linear map, that will be performed on the state in the data register. We develop a mathematical description for these devices, and apply it to several different examples of processors. The problem of finding a processor that will be able to implement a given set of mappings is also examined, and it is shown that, while it is possible to design a finite processor to realize the phase-damping channel, it is not possible to do so for the amplitude-damping channel.