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Acta Aeronautica Et Astronautica Sinica

一种基于矩阵分裂的QC-LDPC码Log-BP译码方法

赵玲, 张晓林

Published Jan 15, 2008• 0 citations
OpenAlex

Abstract

针对高码率的准循环低密度奇偶校验码（QC—LDPC）提出了一种新的高效的log-BP部分并行译码结构，它通过矩阵分裂，将原监督矩阵分裂成多个小的矩阵，使原本的校验节点更新运算被拆分成多次处理，有效地降低了BP迭代运算的复杂度；通过组织不同小矩阵校验节点更新运算与变量节点更新运算的先后顺序，可以使不同小矩阵的校验节点更新运算与变量节点更新运算同时进行，从而提高译码器的译码速率。该方法既适用于非规则码，也适用于规则码。实验结果表明，与现有的log—BP译码方法相比，在相同的码速率下，校验节点更新单元（CNU）与变量节点更新单元（VNU）规模总量减小1／3；在相同的硬件资源下，译码速率提高1／3，另外该方法使CNU与VNu结构趋于对称，有利于设置更少的流水线级数，获得更好的时钟性能。

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针对高码率的准循环低密度奇偶校验码（QC—LDPC）提出了一种新的高效的log-BP部分并行译码结构，它通过矩阵分裂，将原监督矩阵分裂成多个小的矩阵，使原本的校验节点更新运算被拆分成多次处理，有效地降低了BP迭代运算的复杂度；通过组织不同小矩阵校验节点更新运算与变量节点更新运算的先后顺序，可以使不同小矩阵的校验节点更新运算与变量节点更新运算同时进行，从而提高译码器的译码速率。该方法既适用于非规则码，也适用于规则码。实验结果表明，与现有的log—BP译码方法相比，在相同的码速率下，校验节点更新单元（CNU）与变量节点更新单元（VNU）规模总量减小1／3；在相同的硬件资源下，译码速率提高1／3，另外该方法使CNU与VNu结构趋于对称，有利于设置更少的流水线级数，获得更好的时钟性能。
针对PEG（Progressive EdgeGrowth）算法构造的LDPC码在保证局部围长最大时仍有较多数目的小环，提出利用PC（Polynomial of Cycle）标记将PEG算法进行改进为PC-PEG算法，并应用于准循环码（QC-LDPC）中。该方法在满足局部围长尽可能大的前提下，减少了小环数目，提高了译码性能。引入QC-LDPC码的特性，其中校验矩阵是一种分块的循环移位码，该特定结构在工程上可以实现部分并行译码，节省存储空间。实验结果表明，该方法与PEG算法相比具有较少的小环数目，而准循环结构的特点在保证译码性能相当的前提下实现了工程上的部分并行译码。
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.
由于BP算法中的非线性运算较复杂，实现中通常采用Min—Sum近似简化译码算法。针对译码过程中需要存储大量信息的问题，本文提出了一种基于Min—Sum近似算法的QC—LDPC译码器。通过重新安排Min—Sum近似算法中的运算，并将校验节点信息以一种压缩冗余的形式表示，大大减少了译码器所需的存储空间。针对QC—LDPC码校验矩阵准循环的特性，译码过程中以块为单位对信息进行更新，且可以实现多种消息传递调度策略。为进一步减少存储空间，对变量节点信息采用了非线性量化，根据密度演进理论对量化规则进行了优化。
This paper presents a decoding method for regular QC-LDPC codes. In this method, the original check matrix is split into several smaller ones, thus CNU is decomposed into multiple parallel units, which results in great hardware resource reduction. A novel iterative sequence is presented. Compared with the traditional log-BP decode method, the method can reduce the whole logic core size of CNU and VNU by 1/3 under the same bit-rate, and it can improve bit-rate by 1/3 under the same logic core size in the condition of the original check matrix split into two parts.
构造围长较大的校验矩阵,是提高二进制和多进制QC-LDPC码译码性能的一种有效手段.本文提出一种不需要借助于任何计算机搜索步骤,能够直接构造出围长至少为8的QC-LDPC码的显式构造框架.该框架所构造的QC-LDPC码不仅满足围长至少为8的条件,而且还具有循环置换矩阵（CPM）尺寸可以连续变化的优点.该框架可以分为两个步骤：第一步是在无穷大CPM尺寸条件下利用确定性方法构造一个围长至少为8的校验矩阵;第二步是根据本文新发现的一个围长性质,从该校验矩阵的移位矩阵直接精确地计算出CPM尺寸连续变化的紧致下界.
In low-density parity-check (LDPC) code decoding with the iterative sum-product algorithm (SPA), due to the randomness of the parity-check matrix, H, the overlapping of the check node processing unit (CNU) and variable node processing unit (VNU) in the same clock cycle is difficult. The paper demonstrates that overlapped decoding can be exploited as long as the LDPC matrix is composed of identity matrices and their cyclic-shifted matrices, i.e., the parity-check matrix, H, belongs to a class of quasi-cyclic LDPC codes. It is shown that the number of clock cycles required for decoding can be reduced by 50% when overlapped decoding is applied to a (3,6)-regular LDPC code decoder.