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Efficient Decoding Method for Regular QC-LDPC Codes

Ling Zhao, Xiaolin Zhang, Zhu Man-jie

Published Jan 1, 2008• 0 citations
OpenAlex

Abstract

This paper presents a decoding method for regular QC-LDPC codes. In this method, the original check matrix is split into several smaller ones, thus CNU is decomposed into multiple parallel units, which results in great hardware resource reduction. A novel iterative sequence is presented. Compared with the traditional log-BP decode method, the method can reduce the whole logic core size of CNU and VNU by 1/3 under the same bit-rate, and it can improve bit-rate by 1/3 under the same logic core size in the condition of the original check matrix split into two parts.

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Asilomar Conference on Signals, Systems and Computers (ACSSC)•Nov 1, 2014•6 citations
This paper presents a decoding method for regular QC-LDPC codes. In this method, the original check matrix is split into several smaller ones, thus CNU is decomposed into multiple parallel units, which results in great hardware resource reduction. A novel iterative sequence is presented. Compared with the traditional log-BP decode method, the method can reduce the whole logic core size of CNU and VNU by 1/3 under the same bit-rate, and it can improve bit-rate by 1/3 under the same logic core size in the condition of the original check matrix split into two parts.
In this paper, we present a simplification of log-BP algorithm which is able to reduce iterative times of decoding algorithm and save the hardware resource of decoder for LDPC codes. This simplification designs an improved layered-iterative decoding method without reducing the decoding performance, of which speed the updating of check nodes and variable nodes. Simulation results show that the improved layered-iterative log-BP algorithm with six-time iteration exhibits similar decoding performance to the traditional log-BP algorithm with ten-time iteration. When the improved log-BP and traditional log-BP both are simulated in ten-time iteration, the SNR of improved layer-iterative method decreases about 0.25 dB than that of traditional log-BP in the BER of 1e-2.
Quasi cyclic LDPC (QC-LDPC) codes consisting of circulant permutation matrices (CPM-QC-LDPC) are one of the most attractive types of LDPC codes due to their many advantages. In this paper, we mainly do some research on CPM-QC-LDPC codes. We first propose a two-stage decoding scheme mainly based on parity check matrix transform (MT), which can efficiently improve the bit error rate performance. To optimize the tradeoff between hardware implementation complexity and decoding performance, an improved method that combines our proposed MT scheme with the existing CPM-RID decoding scheme is presented. An experiment shows that both schemes can improve the bit error rate (BER) performance. Finally, we show that the MT decoding mechanism can be applied to other types of LDPC codes. We apply the MT scheme to random LDPC codes and show that it can efficiently lower the error floor.
An effective way of improving decoding performance of an LDPC code is to extend the single-decoder decoding method to a parallel decoding method with multiple sub-decoders. To this end, this paper proposes a parallel decoding method for the LDPC codes constructed by m-sequence. In this method, the sub-decoders have two types. The first one contains only one decoding module using the original parity-check constraints to implement a belief propagation (BP) algorithm. The second one consists of a pre-decode module and a decoding module. The parity-check matrices for pre-decode modules are generated by the parity-check constraints of the sub-sequences sampled from an m-sequence. Then, the number of iterations of the BP process in each pre-decode module is set as half of the girth of the parity-check matrix, resulting in the elimination of the impact of short cycles. Using maximum a posterior (MAP), the least metric selector (LMS) finally picks out a codeword from the outputs of sub-decoders. Our simulation results show that the performance gain of the proposed parallel decoding method with five sub-decoders is about 0.4 dB, compared to the single-decoder decoding method at the bit error rate (BER) of 10−5.
In this paper, a combined Low-Density Parity-Check (LDPC) code decoding design method, called modified Block-Type LDPC (B-LDPC), for realistic LDPC coding system architectures is presented. The B-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm owing to the simple structure of their parity-check matrices. A proposed distribution of irregular parity-check matrix for the modified B-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and achievable architecture implementation. The modified B-LDPC code decoding utilizes the iterative min-sum algorithm (MSA) and its decoding architecture design employs the non-overlapping operations of bit node unit (BNU) and check node unit (CNU). Different block matrix sizes for parity-check matrix can be adopted so that the modified B-LDPC code decoding improves the throughput without obvious performance degradation.
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.
This paper presents a reduced-complexity iterative decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes which is devised based on the section-wise cyclic structure of their parity-check matrices. The decoding scheme significantly reduces the hardware implementation complexity of a QC-LDPC code decoder in terms of the number of message processing units and the number of wires required to connect the message processing units. A long high-rate high-performance QC-LDPC code is used to demonstrate the effectiveness of the proposed decoding scheme. Using this long code as the mother code, descendant QC-LDPC codes of various lengths and rates can be constructed by puncturing and masking the columns and rows of the parity-check matrix of the mother code. These descendant codes can be decoded by deactivating specific sets of message processing units of the mother decoder.