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IEICE Transactions on Communications

An Iterative Decoding Scheme for CPM-QC-LDPC Codes Based on Matrix Transform

Zuohong Xu, Jiang Zhu, Cheng Qian, Zixuan Zhang

Published Sep 5, 2018• 3 citations
Publisher

Abstract

Quasi cyclic LDPC (QC-LDPC) codes consisting of circulant permutation matrices (CPM-QC-LDPC) are one of the most attractive types of LDPC codes due to their many advantages. In this paper, we mainly do some research on CPM-QC-LDPC codes. We first propose a two-stage decoding scheme mainly based on parity check matrix transform (MT), which can efficiently improve the bit error rate performance. To optimize the tradeoff between hardware implementation complexity and decoding performance, an improved method that combines our proposed MT scheme with the existing CPM-RID decoding scheme is presented. An experiment shows that both schemes can improve the bit error rate (BER) performance. Finally, we show that the MT decoding mechanism can be applied to other types of LDPC codes. We apply the MT scheme to random LDPC codes and show that it can efficiently lower the error floor.

DOI
10.1587/transcom.2018ebp3177

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Cyclically-coupled quasi-cyclic low-density parity-check (CC-QC-LDPC) codes are a new class of QC-LDPC codes which can achieve excellent error performance and relatively low hardware requirement. In this paper, we modify the CC-QC-LDPC code construction by using random permutation matrices instead of circulant permutation matrices, forming the “random-permutation-matrix-based CC-LDPC (RP-CC-LDPC) code”. The objective is to achieve a better error performance under the same code length. We simulate the bit error rate using FPGA simulations. We also compare the BER results and decoder complexity of the above codes with those of regular and irregular QC-LDPC codes under the same code length and code rate.
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Due to quasi-cyclic structure of parity-check matrices, Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes reduce hardware requirements, and thus they have a higher practical value than random LDPC codes. This paper proposes an improved construction method of QC-LDPC based on PEG Algorithm, and the girth of the QC-LDPC codes has an increase of 2. Firstly, a base matrix is generated by the PEG algorithm, and then the base matrix is expanded using the unit circle permutation matrix, at the same time, the short loop of the base matrix is eliminated. This approach has the advantages of the PEG algorithm and the QC-LDPC codes, and simulation results show that bit error rate (BER) performance of the QC-LDPC codes presented in this paper is the same as or exceeds the one of randomly constructed LDPC codes.
This paper presents a reduced-complexity iterative decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes which is devised based on the section-wise cyclic structure of their parity-check matrices. The decoding scheme significantly reduces the hardware implementation complexity of a QC-LDPC code decoder in terms of the number of message processing units and the number of wires required to connect the message processing units. A long high-rate high-performance QC-LDPC code is used to demonstrate the effectiveness of the proposed decoding scheme. Using this long code as the mother code, descendant QC-LDPC codes of various lengths and rates can be constructed by puncturing and masking the columns and rows of the parity-check matrix of the mother code. These descendant codes can be decoded by deactivating specific sets of message processing units of the mother decoder.
In the paper, we propose a novel construction method for quasi-cyclic (QC) low-density parity-check (LDPC) codes with lower error floor. This approach aims at eliminating the most harmful substructures by choosing proper shift values for cyclic permutation matrices (CPM). To search these harmful substructures, we introduce a high-efficiency searching algorithm, based on cycle combination and leaf cutting. In addition, a high throughput decoding platform based on multi-core CPU with SIMD instruction sets are implemented and utilized to reach the error floors of different LDPC codes efficiently. Simulation results show that for given base matrices, our method can achieve excellent performance in the high SNR region.