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International Conference on Solid State Devices and Materials (SSDM)

Integrated Cryo-CMOS Circuit Systems for Quantum Computing

Jae-Yoon Sim

Published Sep 15, 2026• 0 citations
Publisher
DOI
10.7567/ssdm.2026.m-1-01

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Quantum computing (QC) is a new paradigm that exploits fundamental principles of quantum mechanics, such as superposition and entanglement, to tackle problems in mathematics, chemistry, and material science that are well beyond the reach of supercomputers [1]. Its power is derived from a quantum bit (qubit) that can simultaneously exist in a superposition of both zero and one states and become entangled with other qubits. It has been shown that quantum computers can speed up algorithms and, potentially, model any physical process [2]. QC is now the main driver behind the phenomenal development of cryogenic CMOS, or cryo-CMOS [3]. The starting point was the sudden emergence of rudimentary quantum computers from obscure physics labs [4]. In the past, there was simply no sufficient motivation to go through the pain of designing IC circuits at deep cryogenic temperatures, where the silicon substrate is known to freeze out electrically and where no Spice models exist. Hence, we cannot find any remarkable literature related to cryo-CMOS from back then. Now that cryo-CMOS work has seriously begun, the designed circuits are being deployed for other applications, such as astronomy and physics experiments [5]-[12].
Quantum computers1 could revolutionize computing in a profound way due to the massive speedup they promise. A quantum computer comprises a cryogenic quantum processor and a classical electronic controller. When scaling up the cryogenic quantum processor to at least a few thousands, and possibly millions, of qubits required for any practical quantum algorithm, cryogenic CMOS (cryo-CMOS) electronics is required to allow feasible and compact interconnections between the controller and the quantum processor. Cryo-CMOS leverages the CMOS fabrication infrastructure while exploiting the continuous improvement of performance and miniaturization guaranteed by Moore's law, in order to enable the fabrication of a cost-effective practical quantum computer. However, designing cryo-CMOS integrated circuits requires a new set of CMOS device models, their embedding in design and verification tools, and the possibility to co-simulate the cryo-CMOS/quantum-processor architecture for full-system optimization. In this paper, we address these challenges by focusing on their impact on the design of complex cryo-CMOS systems.