Modern society increasingly depends on ever more capable computing devices. Yet some important problems remain beyond the reach of classical computers due to their inherent computational complexity. At the same time, the energy required to power this growing computational demand is an important concern. Over the past decade, quantum computers have received increased attention, not as a replacement for classical systems, but as a complementary technology with the potential to tackle complex problems more efficiently and significantly boost computational performance. This is made possible by leveraging the principles of quantum mechanics. To achieve this, quantum computers rely on a fundamental basic block called a qubit. There are several different technologies for realizing qubits, and no single approach has yet established itself as the definitive choice. In this work, we focus on silicon spin qubits in quantum dots, which use the intrinsic spin states of an electron as the computational basis states. This platform offers notable advantages including long coherence times, compatibility with the existing semiconductor industry and scalability. However, this technology is still very immature and substantial progress is still required. Just like for the design of classical electronics, simulations can play a crucial role by reducing development cycles, lowering costs, and improving overall efficiency. Throughout this thesis, we will propose a comprehensive simulation framework that allows to study and design spin qubit systems focusing on key aspects of the system architecture. First, a spin qubit compact model is presented that enables the co-simulation of spin qubits together with the classical CMOS control and readout circuitry that will significantly impact the performance of the qubits. We show that the model is capable of including all elements to build an elementary quantum gate set and illustrate its use by co-simulating a spin qubit coupled to a readout resonator with a complete cryo-CMOS readout chip design in a commercial electronic design automation tool. Next, we discuss a hybrid-Hamiltonian simulation approach that is aimed at simulating spin qubit microarchitectures that are suited for running quantum error correction protocols, which protect the encoded information against the errors that unavoidably happen due to the inherently noisy physical qubit devices. This simulation approach incorporates several novel strategies to tackle the challenge of the required computing power that grows exponentially with the size of the simulated system. Furthermore, additional functionality is incorporated to evaluate and track the performance of the implemented error correction protocols. Finally, we propose a characterization protocol for constructing a correlated noise model of the charge noise that is an important factor affecting spin qubit performance. The sources of charge noise are modelled as two-level fluctuators and the entire qubit array is characterized by dividing it into patches and running batches of benchmarking quantum gate sequences. The resulting noise model enables to scale the simulations to larger system sizes and to study the system performance and hardware demands of error correction protocols. Together, these models form a multi-layer simulation framework that enables detailed analysis and optimization of future spin qubit microarchitectures, with particular emphasis on error correction protocols. As such, the framework contributes to the realization of practical large-scale quantum computing.
Modern society increasingly depends on ever more capable computing devices. Yet some important problems remain beyond the reach of classical computers due to their inherent computational complexity. At the same time, the energy required to power this growing computational demand is an important concern. Over the past decade, quantum computers have received increased attention, not as a replacement for classical systems, but as a complementary technology with the potential to tackle complex problems more efficiently and significantly boost computational performance. This is made possible by leveraging the principles of quantum mechanics. To achieve this, quantum computers rely on a fundamental basic block called a qubit. There are several different technologies for realizing qubits, and no single approach has yet established itself as the definitive choice. In this work, we focus on silicon spin qubits in quantum dots, which use the intrinsic spin states of an electron as the computational basis states. This platform offers notable advantages including long coherence times, compatibility with the existing semiconductor industry and scalability. However, this technology is still very immature and substantial progress is still required. Just like for the design of classical electronics, simulations can play a crucial role by reducing development cycles, lowering costs, and improving overall efficiency. Throughout this thesis, we will propose a comprehensive simulation framework that allows to study and design spin qubit systems focusing on key aspects of the system architecture. First, a spin qubit compact model is presented that enables the co-simulation of spin qubits together with the classical CMOS control and readout circuitry that will significantly impact the performance of the qubits. We show that the model is capable of including all elements to build an elementary quantum gate set and illustrate its use by co-simulating a spin qubit coupled to a readout resonator with a complete cryo-CMOS readout chip design in a commercial electronic design automation tool. Next, we discuss a hybrid-Hamiltonian simulation approach that is aimed at simulating spin qubit microarchitectures that are suited for running quantum error correction protocols, which protect the encoded information against the errors that unavoidably happen due to the inherently noisy physical qubit devices. This simulation approach incorporates several novel strategies to tackle the challenge of the required computing power that grows exponentially with the size of the simulated system. Furthermore, additional functionality is incorporated to evaluate and track the performance of the implemented error correction protocols. Finally, we propose a characterization protocol for constructing a correlated noise model of the charge noise that is an important factor affecting spin qubit performance. The sources of charge noise are modelled as two-level fluctuators and the entire qubit array is characterized by dividing it into patches and running batches of benchmarking quantum gate sequences. The resulting noise model enables to scale the simulations to larger system sizes and to study the system performance and hardware demands of error correction protocols. Together, these models form a multi-layer simulation framework that enables detailed analysis and optimization of future spin qubit microarchitectures, with particular emphasis on error correction protocols. As such, the framework contributes to the realization of practical large-scale quantum computing.
The development of future full-scale quantum computers (QCs) not only comprises the design of good quality qubits, but also entails the design of classical complementary metal–oxide semiconductor (CMOS) control circuitry and optimized operation protocols. The construction and implementation of quantum error correction (QEC) protocols, necessary for correcting the errors that inevitably occur in the physical qubit layer, form a crucial step in this design process. The steadily rising numbers of qubits in a single system make the development of small-scale quantum architectures that are able to execute such protocols a pressing challenge. Similar to classical systems, optimized simulation tools can greatly improve the efficiency of the design process. We propose an automated simulation framework for the development of qubit microarchitectures, in which the effects of design choices in the physical qubit layer on the performance of QEC protocols can be evaluated, whereas the focus in the current state-of-the-art design tools only lies on the simulation of the individual quantum gates. The hybrid Hamiltonian framework introduces the innovative combination of a hybrid nature that allows to incorporate several levels throughout the QC stack, with optimized embedded solvers. This provides the level of detail required for an in-depth analysis of the QEC protocol's stability.
The growing interest in quantum computers has triggered various approaches for the realization of a large-scale quantum processor that can eventually outperform classical high-performance computers. Quantum computers are attracting increasing attention for their potential to enormously accelerate the simulation of quantum systems and the solution of optimization problems, promising an immense impact, particularly in fields such as chemistry, medicine, and cybersecurity. Although it is still a long way to a practical quantum device, the progress over the last decades has shown encouraging results for a so far limited number of quantum bits, or qubits for short, which represent the computational units of the processor. One promising platform for the implementation of qubits is the spin of charge carriers in semiconductor quantum dots. Especially the use of purified silicon as a host material has significantly improved the performance of quantum operations. Advanced fabrication techniques from the established semiconductor industry in principle allow for the manufacturing of a large number of qubits on a small chip, making them specifically competitive from the perspective of scalability. In this thesis, we investigate challenges for electron spin qubits, particularly in the context of scaling to large qubit arrays for quantum computation. We evaluate the performance of quantum gates, present error mitigation strategies, and propose new quantum operations for two particular spin qubit implementations. In a dense array of Loss-DiVincenzo spin qubits on a chip, quantum information can be electrically controlled by microwave pulses. For neighboring qubits, capacitive couplings of nearby electrodes lead to crosstalk that affects the quantum computation. The first examination in this thesis addresses the effect of crosstalk on idling and operating spin qubits due to an interfering microwave drive. After the analysis and characterization of the performance, we suggest mitigation protocols for different constellations of important quantum gates, which can be easily implemented experimentally. We further show how to reduce crosstalk in a two-qubit gate using an asymmetric driving scheme, resulting in an enormous improvement of the gate performance, and may be used to generally overcome the obstacle of crosstalk. An additional source of errors in spin qubit registers originates from the finite residual exchange interaction between neighboring qubits. It arises due to a finite overlap of the electron wave functions and is caused by the limited speed at which the applied voltages can be controlled. We evaluate the fidelity of doing quantum operations under these circumstances with a varying number of neighboring qubits and present robust mitigation schemes with a decent performance also in the presence of noise. Besides crosstalk, another crucial observation in experiments using microwaves is the heating caused by the delivery of high-power radio frequency pulses to the quantum chip and results in a change of the qubit properties. We therefore investigate the impact of phonons on the energy levels in spin qubits to identify a temperature-dependent correction to the qubit state splitting. As microwave pulses are associated with potential errors, exchange-only qubits represent a promising alternative to achieve universal quantum computation only using baseband control. Therefore, we shift our focus towards exchange-only qubits and outline the main error sources in these systems, including residual exchange interactions between spins, charge noise from the applied voltages, and magnetic fluctuations in the material. A consequential complication of this implementation is that the quantum information can leak out of the qubit states. This effect, however, can be reduced in the presence of a finite magnetic field, as we will demonstrate in this thesis. The gate construction for exchange-only qubits usually requires more pulse steps than in the previous qubit type. Nevertheless, if exchange interactions are switched on simultaneously, this can result in faster quantum gates, as we demonstrate in this thesis. Especially the discovery of a quantum operation that introduces relative phases between computational and leakage states can be of interest for the construction of two-qubit gates and will be discussed in an example for a special operation space.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.
Semiconductor spin qubits offer a promising route to compact and scalable quantum computers, combining long coherence times in isotopically purified silicon with compatibility with semiconductor manufacturing. Beyond computational speedup, their energy efficiency is an important consideration for future large-scale systems. We evaluate the power and energy requirements of a Loss-DiVincenzo spin-qubit quantum computer by analyzing the Quantum Fourier Transform (QFT) and benchmarking it against the classical Fast Fourier Transform (FFT). We develop a detailed energy budget, identifying cryogenic cooling as the dominant baseline contribution before quantum error correction (QEC). The comparison between the QFT and the classical FFT reveals that, for any quantum workload operating under a polynomially bounded sampling regime, the crossover in energy consumption occurs at smaller problem sizes than the crossover in execution time. Thus, quantum computing can become energetically competitive before achieving a speedup in execution time. We then incorporate surface-code QEC and analyze the energy costs of QEC cycles, gate synthesis, and decoding. At scale, instrumentation and decoding become dominant contributions, while cryogenic cooling imposes a constraint on scalability. We show that optimizing the control-signal demultiplexing ratio can reduce the overall energy cost by approximately two orders of magnitude. For a system with about one million physical qubits, we estimate a power consumption of approximately 100 kW, at least one order of magnitude below that of today's highest-performance classical computing systems.
As quantum processors grow in complexity, the focus is shifting towards the scaling of the entire quantum computing system, including the quantum hardware but as well the classical support electronics. Silicon-based quantum computing offers the enticing possibility that the quantum processor, the quantum-classical interface, and the classical layer can all, in principle, be manufactured using complementary metal-oxide semiconductor (CMOS) technology, creating an opportunity to move from distributed quantum-classical systems to integrated quantum computing solutions. Here, we review the state-of-the-art in spin-based quantum computing in silicon and present different approaches to help scale the technology using CMOS technology. We discuss the use of industry-manufactured silicon devices as the basic qubit element and present radio-frequency reflectometry techniques for fast high-fidelity spin readout. Finally, we show how quantum-classical co-integration can enable large-scale control and readout via frequency- and time-domain multiplexing.