The development of future full-scale quantum computers (QCs) not only comprises the design of good quality qubits, but also entails the design of classical complementary metal–oxide semiconductor (CMOS) control circuitry and optimized operation protocols. The construction and implementation of quantum error correction (QEC) protocols, necessary for correcting the errors that inevitably occur in the physical qubit layer, form a crucial step in this design process. The steadily rising numbers of qubits in a single system make the development of small-scale quantum architectures that are able to execute such protocols a pressing challenge. Similar to classical systems, optimized simulation tools can greatly improve the efficiency of the design process. We propose an automated simulation framework for the development of qubit microarchitectures, in which the effects of design choices in the physical qubit layer on the performance of QEC protocols can be evaluated, whereas the focus in the current state-of-the-art design tools only lies on the simulation of the individual quantum gates. The hybrid Hamiltonian framework introduces the innovative combination of a hybrid nature that allows to incorporate several levels throughout the QC stack, with optimized embedded solvers. This provides the level of detail required for an in-depth analysis of the QEC protocol's stability.
The development of future full-scale quantum computers (QCs) not only comprises the design of good quality qubits, but also entails the design of classical complementary metal–oxide semiconductor (CMOS) control circuitry and optimized operation protocols. The construction and implementation of quantum error correction (QEC) protocols, necessary for correcting the errors that inevitably occur in the physical qubit layer, form a crucial step in this design process. The steadily rising numbers of qubits in a single system make the development of small-scale quantum architectures that are able to execute such protocols a pressing challenge. Similar to classical systems, optimized simulation tools can greatly improve the efficiency of the design process. We propose an automated simulation framework for the development of qubit microarchitectures, in which the effects of design choices in the physical qubit layer on the performance of QEC protocols can be evaluated, whereas the focus in the current state-of-the-art design tools only lies on the simulation of the individual quantum gates. The hybrid Hamiltonian framework introduces the innovative combination of a hybrid nature that allows to incorporate several levels throughout the QC stack, with optimized embedded solvers. This provides the level of detail required for an in-depth analysis of the QEC protocol's stability.
This paper explores the potential of simulating topological qubits within computer networks as a viable strategy for quantum error correction (QEC). The core argument presented is that simulating topological qubits provides a scalable pathway to QEC, circumventing the significant challenges associated with the physical fabrication and maintenance of actual topological qubits. The work details the development of a network simulation environment designed to implement the fundamental principles of topological QEC. Specifically, it focuses on designing and testing encoding and decoding schemes for a simulated topological code. The research represents a computationally feasible approach to QEC prior to the realization of practical topological qubits, offering a valuable tool for theoretical exploration and algorithm development within the field of quantum computing. The simulation framework allows for investigating complex error dynamics and optimizing correction protocols in a controlled environment, ultimately contributing to a deeper understanding of topological QEC and its potential for future implementation.
Modern society increasingly depends on ever more capable computing devices. Yet some important problems remain beyond the reach of classical computers due to their inherent computational complexity. At the same time, the energy required to power this growing computational demand is an important concern. Over the past decade, quantum computers have received increased attention, not as a replacement for classical systems, but as a complementary technology with the potential to tackle complex problems more efficiently and significantly boost computational performance. This is made possible by leveraging the principles of quantum mechanics. To achieve this, quantum computers rely on a fundamental basic block called a qubit. There are several different technologies for realizing qubits, and no single approach has yet established itself as the definitive choice. In this work, we focus on silicon spin qubits in quantum dots, which use the intrinsic spin states of an electron as the computational basis states. This platform offers notable advantages including long coherence times, compatibility with the existing semiconductor industry and scalability. However, this technology is still very immature and substantial progress is still required. Just like for the design of classical electronics, simulations can play a crucial role by reducing development cycles, lowering costs, and improving overall efficiency. Throughout this thesis, we will propose a comprehensive simulation framework that allows to study and design spin qubit systems focusing on key aspects of the system architecture. First, a spin qubit compact model is presented that enables the co-simulation of spin qubits together with the classical CMOS control and readout circuitry that will significantly impact the performance of the qubits. We show that the model is capable of including all elements to build an elementary quantum gate set and illustrate its use by co-simulating a spin qubit coupled to a readout resonator with a complete cryo-CMOS readout chip design in a commercial electronic design automation tool. Next, we discuss a hybrid-Hamiltonian simulation approach that is aimed at simulating spin qubit microarchitectures that are suited for running quantum error correction protocols, which protect the encoded information against the errors that unavoidably happen due to the inherently noisy physical qubit devices. This simulation approach incorporates several novel strategies to tackle the challenge of the required computing power that grows exponentially with the size of the simulated system. Furthermore, additional functionality is incorporated to evaluate and track the performance of the implemented error correction protocols. Finally, we propose a characterization protocol for constructing a correlated noise model of the charge noise that is an important factor affecting spin qubit performance. The sources of charge noise are modelled as two-level fluctuators and the entire qubit array is characterized by dividing it into patches and running batches of benchmarking quantum gate sequences. The resulting noise model enables to scale the simulations to larger system sizes and to study the system performance and hardware demands of error correction protocols. Together, these models form a multi-layer simulation framework that enables detailed analysis and optimization of future spin qubit microarchitectures, with particular emphasis on error correction protocols. As such, the framework contributes to the realization of practical large-scale quantum computing.
Quantum error correction (QEC) enables reliable computation on noisy hardware by encoding logical information across many physical qubits and periodically measuring parities to detect errors. A decoder is the classical algorithm that uses these measurements to infer which error most likely occurred, so that the system can correct it. The decoder's accuracy-how rarely it makes the wrong guess-directly determines the scale of quantum computation that can be reliably executed. With a wealth of competing decoding algorithms, a QEC system designer needs reliable methods to evaluate them. Today, the dominant approach is to evaluate decoders using Monte Carlo simulation. However, simulation has several drawbacks such as requiring many samples to produce low variance estimates.
In this work, we develop a new systematic analysis for evaluating decoders. We introduce a novel formal semantics of a core language for QEC programs that captures the de facto standard Stim circuit format, providing a principled theoretical foundation for the emerging space of fault-tolerant quantum systems design. Given a QEC program and a decoder, our verifier can quantify both the decoder accuracy and the decoder robustness to drift in physical error rate. Our approach has two key components: (i) a structured search over the space of possible errors; and (ii) a constrained polynomial optimization kernel. A thorough empirical evaluation of our approach suggests that it can outperform simulation, especially in low error rate regimes, and that it can be deployed to quantify decoder robustness over an interval of physical error rates.
Abstract The immense resource overhead of full quantum error correction (QEC) presents a formidable barrier to achiev- ing fault-tolerant quantum computation. This paper introduces a hybrid analog-digital quantum processor architecture designed as a pragmatic strategy for achieving ”mid-scale fault tolerance” (MSFT). We formally define MSFT as a hardware-level error suppression scheme that achieves a fidelity gain by replacing deep, error-prone digital gate sequences with single, high-fidelity analog evolution blocks. The architecture comprises a programmable digital core for state preparation and measurement, coupled to an analog co-processor that executes computationally intensive Hamiltonian evolutions. This approach reduces the effective logical depth and error accumulation for algorithms like VQE. We validate this claim with statistically robust simulations on standard molecular Hamiltonians (LiH and BeH), demonstrating a significant performance advantage over purely digital systems based on an aggregation of 50 independent simulation trials. The analysis includes scalability and a discussion of the critical digital-analog interface, proposing trapped-ion and neutral-atom systems as viable physical platforms
This paper investigates the potential of leveraging quantum error correction (QEC) codes within a hardware-accelerated quantum computing architecture. The core claim centers around designing a system that utilizes the inherent error-correcting capabilities of QEC codes to dramatically improve the robustness and computational efficiency of quantum computations. The proposed mechanism involves tightly integrating specific QEC codes with tailored hardware designs, employing hardware acceleration techniques to expedite the computationally intensive error correction encoding and decoding processes. The novelty lies in translating the theoretical advantages of QEC codes into tangible hardware acceleration benefits, thereby significantly enhancing the practicality and scalability of quantum computing. We explore the fundamental principles, architectural considerations, and potential performance gains associated with this approach, focusing on the reduction of logical qubit decoherence and the optimization of quantum gate operations. This work provides a framework for future research and development in building fault-tolerant quantum computers.
The demonstration of quantum error correction (QEC) is one of the most important milestones in the realization of fully-fledged quantum computers. Toward this, QEC experiments using the surface codes have recently been actively conducted. However, it has not yet been realized to protect logical quantum information beyond the physical coherence time. In this work, we performed a full simulation of QEC for the rotated surface codes with a code distance 5, which employs 49 qubits and is within reach of the current state-of-the-art quantum computers. In particular, we evaluate the logical error probability in a realistic noise model that incorporates not only stochastic Pauli errors but also coherent errors due to a systematic control error or unintended interactions. While a straightforward simulation of 49 qubits is not tractable within a reasonable computational time, we reduced the number of qubits required to 26 qubits by delaying the syndrome measurement in simulation. This and a fast quantum computer simulator, , implemented on GPU allows us to simulate full QEC with an arbitrary local noise within reasonable simulation time. Based on the numerical results, we also construct and verify an effective model to incorporate the effect of the coherent error into a stochastic noise model. This allows us to understand what the effect coherent error has on the logical error probability on a large scale without full simulation based on the detailed full simulation of a small scale. The present simulation framework and effective model, which can handle arbitrary local noise, will play a vital role in clarifying the physical parameters that future experimental QEC should target. Published by the American Physical Society 2024