Hardware validation on IBM’s 133-qubit Heron processor demonstrates that a quantum neural architecture can reliably distinguish neural configurations with 99.3% discrimination quality. The A-Gate circuit encodes excitatory-inhibitory dynamics from EEG signals using paired qubits, achieving O(M) gate complexity for M-channel correlation encoding versus $$O(M^2)$$ classical computation on the symmetric positive definite (SPD) manifold. Transpilation to native CZ gates follows the predicted linear law over the implemented range ( $$14.1M - 17.5$$ , $$R^2 > 0.99$$ for $$M \le 8$$ ); extending to $$M = 32$$ reveals super-linear growth from topology-induced routing overhead, which we report as a hardware limitation distinct from the architecture’s O(M) logical complexity. Evaluation on the CHB-MIT Scalp EEG Database using leave-one-subject-out (LOSO) cross-validation across 22 subjects reveals a critical encoding bottleneck: the quantum fidelity classifier achieves 53.4% AUC compared to 62.5% for an 8-channel classical baseline. Notably, per-subject AUC ranges from 0.183 to 1.000, with sub-chance performance in some cases suggesting what we term manifold polarity, a hypothesized patient-specific geometric orientation that may cause cross-subject template mismatch. The gap between quantum and classical performance indicates that mapping EEG features to circuit parameters, not the A-Gate architecture itself, limits classification. We provide complexity analysis with corrections to common quantum-advantage overclaims, and we are explicit that the present results establish hardware feasibility and the location of the performance bottleneck rather than clinical utility.
Hardware validation on IBM’s 133-qubit Heron processor demonstrates that a quantum neural architecture can reliably distinguish neural configurations with 99.3% discrimination quality. The A-Gate circuit encodes excitatory-inhibitory dynamics from EEG signals using paired qubits, achieving O(M) gate complexity for M-channel correlation encoding versus O(M2) classical computation on the symmetric positive definite (SPD) manifold. Transpilation to native CZ gates follows the predicted linear law over the implemented range ( 14.1M−17.5 , R2>0.99 for M≤8 ); extending to M=32 reveals super-linear growth from topology-induced routing overhead, which we report as a hardware limitation distinct from the architecture’s O(M) logical complexity. Evaluation on the CHB-MIT Scalp EEG Database using leave-one-subject-out (LOSO) cross-validation across 22 subjects reveals a critical encoding bottleneck: the quantum fidelity classifier achieves 53.4% AUC compared to 62.5% for an 8-channel classical baseline. Notably, per-subject AUC ranges from 0.183 to 1.000, with sub-chance performance in some cases suggesting what we term manifold polarity, a hypothesized patient-specific geometric orientation that may cause cross-subject template mismatch. The gap between quantum and classical performance indicates that mapping EEG features to circuit parameters, not the A-Gate architecture itself, limits classification. We provide complexity analysis with corrections to common quantum-advantage overclaims, and we are explicit that the present results establish hardware feasibility and the location of the performance bottleneck rather than clinical utility.
This paper presents a quantum computing architecture for multi-channel electroencephalogram (EEG) analysis based on the Positive-Negative (PN) neuron model. The architecture encodes excitatory-inhibitory dynamics using paired qubits with parameterized rotation gates, achieving O(M) gate complexity for M-channel correlation encoding compared to O(M 2) classical pairwise computation. Hardware validation on IBM's 133-qubit Heron processor (ibm_torino) confirms the theoretical scaling with measured two-qubit gate counts following 14.1M − 17.5, and demonstrates 99.3% discrimination quality between five distinct neural configurations. Evaluation on the CHB-MIT Scalp EEG Database (22 subjects, leave-one-subject-out cross-validation) establishes empirical performance bounds: the quantum fidelity classifier achieves 53.4% AUC compared to 62.5% for an 8-channel classical baseline and 81.98% for an 18-channel XGBoost classifier. These results reveal that the encoding strategy-rather than the quantum circuit architecture-constitutes the primary performance bottleneck. The paper contributes: (1) rigorous complexity analysis with explicit corrections to common quantum advantage overclaims; (2) the first hardware validation of a quantum neural architecture on a 133-qubit processor; and (3) honest assessment of current limitations alongside a roadmap for achieving practical utility.
Despite rapid progress in quantum optimization, broad real-hardware benchmarks comparing multiple algorithmic families across diverse combinatorial problems under a common protocol remain limited. We benchmark gate-based quantum optimization on four NP-hard problems: multi-dimensional knapsack (MDKP), maximum independent set (MIS), quadratic assignment (QAP), and market-share (MSP). We study VQE, CVaR-VQE, standard, multi-angle, and warm-start QAOA, together with qubit-efficient PCE and QRAO, on IBM Heron r1/r2 processors using resilience-level-2 mitigation. To our knowledge, this includes the first real-hardware QRAO results and the first multi-problem PCE hardware benchmark.
Across 247 method-instance combinations, we report transpiled circuit size, hardware outcomes, and an independent-error gate-count fidelity proxy, Fest. For MDKP and MIS, an empirical operating point near Fest≈0.1, corresponding to about 770 two-qubit gates at the median Heron-r2 CZ error rate, marks the onset of noise-dominated execution. QAP exposes a separate bottleneck: dense one-hot encodings and an exponentially sparse feasible manifold, with feasible fraction 10!/2100 at n=10; no tested hardware method produces a feasible assignment. Compiled QAOA-family circuits are generally noise dominated, and a matched uniform-random control shows that most feasible low-fidelity outcomes fall within the random range, apart from one finite-sample MIS warm-start exception. A SWAP-aware, fractional-gate, Nighthawk-topology compilation counterfactual reduces two-qubit counts but leaves all circuits below Fest=10−3. These conclusions apply to the tested implementations rather than QAOA in general. Qubit-efficient methods extend runnable instance sizes, but only within the empirical fidelity budget.
Abstract Claims of quantum advantage in machine learning often rest on classical comparators that lack the same features, on simulation alone, and on unreported hardware cost. QBioBench is a benchmark of quantum machine learning on peripheral biosignals that holds quantum and classical models to the same features and reports calibration and hardware cost. It comprises three clinical tasks, 12-lead ECG diagnosis (PTB-XL), single-lead apnea detection (Apnea-ECG), and wearable stress detection, each reduced to six to eight shared dimensions. A factorial grid of projected and fidelity quantum kernels and variational classifiers is screened in noisy simulation, and the promoted configurations are evaluated in an exploratory study on an IBM Nighthawk r2 processor on the full test pools of 510 apnea minutes and 512 PTB-XL records. Every prediction is recovered from the device records, intervals resample recordings or patients, and classical baselines are trained on the same units and tested on the same executed inputs. No quantum model reaches its matched support vector machine in ROC-AUC on either primary task, and none is separably better in balanced accuracy. The angle-encoded fidelity and projected kernels reach ROC-AUC 0.697 and 0.693 on apnea, paired differences of − 0.127 and − 0.119 to the support vector machine, and both are classical by construction, since the entangling layer of the encoding cancels from the fidelity kernel and leaves closed-form local expectations in the projected kernel. A variational classifier comes closest, reaching 0.797 on apnea (difference − 0.012 , 95% interval [ − 0.052 , + 0.027 ] ), and falls to chance without its two-qubit gates. Test sets of the size that circuit budgets favor are unreliable, as random 80-minute subsets of the apnea pool give the fidelity kernel a central 95% range of ROC-AUC from 0.589 to 0.797. Readout mitigation changed ROC-AUC by at most 0.015.
Variational quantum classifiers combine parameterised quantum circuits with classical optimisa-tion to perform supervised classification, but their practical performance depends strongly on circuit architecture, trainability, and hardware-resource requirements. Current noisy intermediate-scalequantum devices further constrain these models through limited usable circuit depth, hardwarenoise, and expensive quantum-circuit evaluations, motivating systematic benchmarking undercontrolled conditions.This thesis investigates how the structure of an interaction-based ansatz influences the behaviourof a hybrid quantum–classical classifier. A ZZ-only IsingZZ ansatz is compared with the proposed Arivoli ansatz, which combines XX-, Y Y -, and ZZ-type interaction channels between neigh-bouring qubits. The primary architecture comparison uses IsingZZ with three repeated nearest-neighbour ladders and Arivoli with one ladder, with nine nominal optimisation parameters in each implementation.Classical data are reduced to four features and encoded on four qubits using arcsin-RY rotations.The resulting quantum states are processed by the parameterised ansatz and measured usingAll-Qubit Multi-Observable Measurement (AMM), producing X-, Y -, and Z-expectation valuesthat are classified by a linear softmax readout. The architectures are evaluated on benchmark classification datasets using predictive performance, optimisation behaviour, expressibility, en-tangling capability, and circuit-resource metrics. Classical baselines and IBM Quantum execution are additionally used to assess the practical relevance and hardware behaviour of the proposedframework.The study does not seek to demonstrate quantum advantage. Instead, it examines the trade-offs between representational capability, optimisation behaviour, classification performance, and hard-ware cost in variational quantum classifier design. The results are used to assess whether richer multi-axis interactions provide practically useful behaviour under near-term quantum-computingconstraints.
We apply the inZOR-ND bio-adaptive genomic discovery engine to quantum error correction (QEC) on real IBM Quantum hardware, without implementing any known QEC code structure. Two versions are presented: v1 (21 Ry parameters, X-only correction with 8 syndromes, 4 test states) and v2 (42 Ry+Rz parameters, Full Pauli correction with 22 syndromes, 6 test states, multi-noise training over 4 CZ error rate levels). Both versions discover hardware-native 7-qubit encoding circuits optimized for the IBM Heron processor's tree topology (ibm_fez physical qubits 3, 2, 4, 16, 1, 5, 23). Across 7 hardware runs on ibm_fez and ibm_marrakesh, inZOR-ND outperforms Steane [[7,1,3]] in all observed hardware runs, with gains from +0.2 to +5.1 percentage points. The key finding is not that inZOR-ND produces a theoretically superior code — in ideal depolarizing noise simulation, Steane's Full Pauli correction remains stronger at all tested noise levels. Rather, these results suggest that genomic search can discover hardware-native QEC encoders whose reduced transpiled cost yields consistent advantage over theoretically stronger but hardware-mismatched codes on NISQ devices. This demonstrates that theoretical optimality is not the same as hardware optimality on current processors. The core hardware advantage: inZOR-ND's native CZ circuits transpile to depth ~53–58 on IBM Heron, while the Steane code (CNOT-based) transpiles to ~115, because CZ is a native IBM Heron gate while CNOT requires decomposition. v2 Rz gates are virtual (zero depth, zero error) on Heron. v1 LUPA precision zoom: simulation fidelity 0.999843 (p_cz=0.002, X-only, 3 rounds × 20 cycles, ~5 min). v2 Qiskit AerSimulator cross-validation: perfect match with NumPy simulator (diff < 1e-16). Key results: - inZOR-ND outperforms Steane in 7/7 observed hardware runs - v1 sim fidelity (LUPA): 0.999843 - v2 sim fidelity (multi-noise avg, Full Pauli): 0.990244 - Best hardware gain vs Steane: +5.1 pp (ibm_marrakesh, noisy regime) - v1 transpiled depth: ~53 | v2: ~58 | Steane: ~115 (IBM Heron) - v1: 21 params (Ry) | v2: 42 params (Ry+Rz) | 12 CZ gates - v2 syndromes: 22 (Full Pauli: I + 7X + 7Y + 7Z) - 8000 shots per circuit, SamplerV2 runtime API
Quantum neural networks are a popular realization of quantum machine learning. Typically, classical data is first embedded into the state vector of a quantum system. A parameterized quantum circuit (PQC) then acts on the quantum state, with its trainable parameters continuously adjusted during the optimization process. However, current quantum hardware faces challenges, such as accumulating noise with increasing circuit complexity and a limited set of native gate operations. As a result, transpiling quantum circuits to real hardware often increases the number of the required gate instructions. These factors set considerable constraints on the accuracy of quantum machine learning models. To address these limitations, we propose a novel quantum neural network architecture, termed hardware-native parameterized quantum embedding (HN-PQE). Our approach offers two key advantages: First, HN-PQE exclusively employs the native gates of IBM's current Eagle quantum processor family, ensuring that the gate count remains stable during transpilation. Second, by combining data embedding with the PQC, HN-PQE achieves a highly compact circuit design. We empirically validate our approach on two classification tasks, simulating both idealized (no hardware noise) and noisy conditions (mimicking IBM's Brisbane device). When compared to two popular quantum neural networks, HN-PQE showed similar performance in idealized scenarios but demonstrated significant noise resilience under hardware-noise conditions. This resilience makes HN-PQE a promising candidate for future quantum machine learning experiments on real hardware.