We apply the inZOR-ND bio-adaptive genomic discovery engine to quantum error correction (QEC) on real IBM Quantum hardware, without implementing any known QEC code structure. Two versions are presented: v1 (21 Ry parameters, X-only correction with 8 syndromes, 4 test states) and v2 (42 Ry+Rz parameters, Full Pauli correction with 22 syndromes, 6 test states, multi-noise training over 4 CZ error rate levels). Both versions discover hardware-native 7-qubit encoding circuits optimized for the IBM Heron processor's tree topology (ibm_fez physical qubits 3, 2, 4, 16, 1, 5, 23). Across 7 hardware runs on ibm_fez and ibm_marrakesh, inZOR-ND outperforms Steane [[7,1,3]] in all observed hardware runs, with gains from +0.2 to +5.1 percentage points. The key finding is not that inZOR-ND produces a theoretically superior code — in ideal depolarizing noise simulation, Steane's Full Pauli correction remains stronger at all tested noise levels. Rather, these results suggest that genomic search can discover hardware-native QEC encoders whose reduced transpiled cost yields consistent advantage over theoretically stronger but hardware-mismatched codes on NISQ devices. This demonstrates that theoretical optimality is not the same as hardware optimality on current processors. The core hardware advantage: inZOR-ND's native CZ circuits transpile to depth ~53–58 on IBM Heron, while the Steane code (CNOT-based) transpiles to ~115, because CZ is a native IBM Heron gate while CNOT requires decomposition. v2 Rz gates are virtual (zero depth, zero error) on Heron. v1 LUPA precision zoom: simulation fidelity 0.999843 (p_cz=0.002, X-only, 3 rounds × 20 cycles, ~5 min). v2 Qiskit AerSimulator cross-validation: perfect match with NumPy simulator (diff < 1e-16). Key results: - inZOR-ND outperforms Steane in 7/7 observed hardware runs - v1 sim fidelity (LUPA): 0.999843 - v2 sim fidelity (multi-noise avg, Full Pauli): 0.990244 - Best hardware gain vs Steane: +5.1 pp (ibm_marrakesh, noisy regime) - v1 transpiled depth: ~53 | v2: ~58 | Steane: ~115 (IBM Heron) - v1: 21 params (Ry) | v2: 42 params (Ry+Rz) | 12 CZ gates - v2 syndromes: 22 (Full Pauli: I + 7X + 7Y + 7Z) - 8000 shots per circuit, SamplerV2 runtime API
We apply the inZOR-ND bio-adaptive genomic discovery engine to quantum error correction (QEC) on real IBM Quantum hardware, without implementing any known QEC code structure. Two versions are presented: v1 (21 Ry parameters, X-only correction with 8 syndromes, 4 test states) and v2 (42 Ry+Rz parameters, Full Pauli correction with 22 syndromes, 6 test states, multi-noise training over 4 CZ error rate levels). Both versions discover hardware-native 7-qubit encoding circuits optimized for the IBM Heron processor's tree topology (ibm_fez physical qubits 3, 2, 4, 16, 1, 5, 23). Across 7 hardware runs on ibm_fez and ibm_marrakesh, inZOR-ND outperforms Steane [[7,1,3]] in all observed hardware runs, with gains from +0.2 to +5.1 percentage points. The key finding is not that inZOR-ND produces a theoretically superior code — in ideal depolarizing noise simulation, Steane's Full Pauli correction remains stronger at all tested noise levels. Rather, these results suggest that genomic search can discover hardware-native QEC encoders whose reduced transpiled cost yields consistent advantage over theoretically stronger but hardware-mismatched codes on NISQ devices. This demonstrates that theoretical optimality is not the same as hardware optimality on current processors. The core hardware advantage: inZOR-ND's native CZ circuits transpile to depth ~53–58 on IBM Heron, while the Steane code (CNOT-based) transpiles to ~115, because CZ is a native IBM Heron gate while CNOT requires decomposition. v2 Rz gates are virtual (zero depth, zero error) on Heron. v1 LUPA precision zoom: simulation fidelity 0.999843 (p_cz=0.002, X-only, 3 rounds × 20 cycles, ~5 min). v2 Qiskit AerSimulator cross-validation: perfect match with NumPy simulator (diff < 1e-16). Key results: - inZOR-ND outperforms Steane in 7/7 observed hardware runs - v1 sim fidelity (LUPA): 0.999843 - v2 sim fidelity (multi-noise avg, Full Pauli): 0.990244 - Best hardware gain vs Steane: +5.1 pp (ibm_marrakesh, noisy regime) - v1 transpiled depth: ~53 | v2: ~58 | Steane: ~115 (IBM Heron) - v1: 21 params (Ry) | v2: 42 params (Ry+Rz) | 12 CZ gates - v2 syndromes: 22 (Full Pauli: I + 7X + 7Y + 7Z) - 8000 shots per circuit, SamplerV2 runtime API
We present noisebridge, an open-source quantum error correction (QEC) SDK implementing a Syndrome Neural Network (SNN) decoder based on a centering-matrix architecture. We report the first published result of zero decoder overhead on real IBM quantum hardware: on IBM Kingston (156-qubit Heron r2 processor, heavy-hex topology), a Z-only rotated surface code of distance d=3 achieves LER_SNN = LER_raw = 0.0422 at p=0.25 — the SNN decoder introduces no additional logical error rate beyond the irreducible hardware noise floor. At p=0.10 the SNN achieves a 1.72x improvement over the standard minimum-weight lookup decoder (LER_SNN=0.0457 vs LER_std=0.0784). A critical architectural insight enables these results: the initial state |0>^9 is not an eigenstate of X-stabilizers, rendering X-syndrome measurement pure noise that inflates circuit depth from 26 to 242 in standard implementations. By restricting to Z-stabilizer measurement only (13 qubits, depth 26, CZ=25, SWAP=0), syndrome accuracy reaches 83.3%, allowing the SNN to bridge the remaining gap to the fault-tolerance threshold. Key results:- Circuit depth: 26 (vs 242 in prior versions, -89%)- Two-qubit gates: CZ=25 (vs CZ=153, -84%)- Z-syndrome accuracy: 83.3% at p=0.10 / 82.5% at p=0.25- LER_SNN = 0.0457 (1.72x over std decoder) at p=0.10- LER_SNN = LER_raw = 0.0422 (zero overhead) at p=0.25- Hardware: IBM Kingston, 13 May 2026 All experiments executed on live IBM hardware. Code available at github.com/noisebridge under MIT license.
Despite rapid progress in quantum optimization, broad real-hardware benchmarks comparing multiple algorithmic families across diverse combinatorial problems under a common protocol remain limited. We benchmark gate-based quantum optimization on four NP-hard problems: multi-dimensional knapsack (MDKP), maximum independent set (MIS), quadratic assignment (QAP), and market-share (MSP). We study VQE, CVaR-VQE, standard, multi-angle, and warm-start QAOA, together with qubit-efficient PCE and QRAO, on IBM Heron r1/r2 processors using resilience-level-2 mitigation. To our knowledge, this includes the first real-hardware QRAO results and the first multi-problem PCE hardware benchmark.
Across 247 method-instance combinations, we report transpiled circuit size, hardware outcomes, and an independent-error gate-count fidelity proxy, Fest. For MDKP and MIS, an empirical operating point near Fest≈0.1, corresponding to about 770 two-qubit gates at the median Heron-r2 CZ error rate, marks the onset of noise-dominated execution. QAP exposes a separate bottleneck: dense one-hot encodings and an exponentially sparse feasible manifold, with feasible fraction 10!/2100 at n=10; no tested hardware method produces a feasible assignment. Compiled QAOA-family circuits are generally noise dominated, and a matched uniform-random control shows that most feasible low-fidelity outcomes fall within the random range, apart from one finite-sample MIS warm-start exception. A SWAP-aware, fractional-gate, Nighthawk-topology compilation counterfactual reduces two-qubit counts but leaves all circuits below Fest=10−3. These conclusions apply to the tested implementations rather than QAOA in general. Qubit-efficient methods extend runnable instance sizes, but only within the empirical fidelity budget.
We report the first experimental validation of the merkabit dual-spinor architecture across four circuit families on IBM ibm_strasbourg (Eagle r3, 127 qubits), executed 6–7 April 2026. The central discovery is that the merkabit's defining operation — the P gate, applying asymmetric phase to counter-rotating spinors — compiles to two native Rz gates with opposite signs: P(φ) = Rz(+φ) ⊗ Rz(−φ). On IBM Eagle r3, both Rz gates are virtual-Z frame changes requiring zero duration, zero error, and zero additional circuit depth. The P gate is native. Eight independent hardware results confirm the architecture, spanning 2 to 26 qubits: Ouroboros return fidelity ZP-ORF = 0.968, transpiler confirming U₀†U₀ = I at depth 1 π-lock standing wave ⟨ZZ⟩ = +0.44 vs +0.447 ideal (2% agreement, two independent runs) Parity witness ⟨XX⟩ = −0.450, consistent with |Φ⁻⟩-like entanglement at 90° Bloch separation Z₂ chirality symmetry mean error 0.016 across n = 4, 6, 8, 12 — all below readout noise threshold; non-monotonic ⟨ZZ⟩ breathing confirmed as standing-wave signature Two-scale Fano structure (9-qubit triangle): intra-round Fano F ≈ 0.52–0.54, within-τ dispersion σ ≤ 0.004 across 18 hardware rounds at τ ∈ {1, 5, 12} Inter-round coherence ρ ≈ 0.86 on the same triangle cell, confirming the two-scale standing-wave memory signature predicted by Paper 15 Full pentachoric error detection (26-qubit, 7-node Eisenstein cell): detection rate 0.089 (baseline) → 0.988 (injected), a 89.9 pp jump; 28/28 single-gate injections above 97% Centre-node syndrome weight 2× periphery matching Eisenstein lattice coordination; sub-Poissonian Fano on every injection (F_centre = 0.055 ± 0.009, F_periphery ≈ 0.20); Z₂ chirality symmetry confirmed inside the Fano structure Four of seven formal predictions from earlier papers in the series are retired by hardware data: P3 (Z₂ symmetry, mean error 0.016 vs <5% threshold), P4 (centre-node detection rate, 99.3% vs 91% ± 5% predicted, exceeding the upper tolerance by 3.3 pp), rotation-gap flatness, and two-scale Fano separation. Three predictions (P1 Berry phase, P2 quasi-period, P5 DTC robustness) remain pending for a subsequent session. A cross-platform reanalysis of Google Quantum AI's 420-experiment Willow dataset shows the opposite sign on every metric (F = 2.42 super-Poissonian, super-linear burst scaling, positive spatial correlation), consistent with a topology distinction: IBM heavy-hex maps naturally onto the Eisenstein lattice; Willow's square grid does not. No error mitigation, post-selection, or parameter tuning was applied to any primary result. Keywords: merkabit, dual spinor, P gate, quantum error correction, sub-Poissonian statistics, Eisenstein lattice, pentachoric code, IBM Eagle r3, Google Willow, standing wave, π-lock, Z₂ symmetry, Fano factor, Floquet time crystal
Quantum computers hold the promise to solve some hard problems that are intractable for even the most powerful current supercomputers. One of the most famous examples is Shor's algorithm for factorizing large numbers, which has exponential speedup compared to its best classical counterparts. However, running such an algorithm will require to build a large-scale quantum computer consisting of thousands or even millions of qubits that include quantum error correction (QEC) and fault-tolerant (FT) mechanisms. Quantum computing is already a reality with the so-called Noisy Intermediate-Scale Quantum (NISQ) processors, some of them available in the cloud. Noisy refers to the imperfect control over the qubits and intermediate-scale to the relatively low number of quits (from fifty to a few hundred). Although current and near-term quantum devices will not have enough qubits for implementing large and fully corrected quantum computations, the use of small quantum error correction codes may extend the computation lifetime of NISQ devices. In this context and as a first step, it is important to test and demonstrate the fault-tolerance of these QEC codes. In this thesis, we explore the fault-tolerance of two small quantum correction codes that are good candidates to be applied to NISQ processors, the [[4,2,2]] code and the [[7,1,3]] Steane code. To this purpose, by following the FT criterion prosed by Daniel Gottesman in 2016, we tested both codes using two simulators, the stabilizer formalism simulator that includes quite simple error models and a full density matrix simulator called quantumsim, which includes more realistic noise. The simulations are performed under reasonable noise parameter values. For the [[4,2,2]] code, 235 circuits are tested based on the two simulators. The results show that in the stabilizer formalism simulation, the FT criterion is satised for all circuits, while not fully satisfied in the full density matrix simulation. For the [[7,1,3]] Steane code, we use a parallel-flag error correction implementation which is tested using the full density matrix simulator. Our results show that without applying any QEC cycle, for all circuits (84 circuits for 1 logical qubit simulation and 452 circuits for 2 logical qubits simulation), the error rate of the encoded circuits is lower than the unencoded ones. Adding a quantum error correction (QEC) cycle will in general increase the error rate of the computation.
Quantum processors have crossed the one-hundred-qubit mark, but noise continues to limit circuit performance, while full quantum error correction remains too costly for routine use. Error suppression and mitigation therefore play an important role in extracting value from current hardware, yet independent comparisons of commercial solutions on identical workloads and devices remain scarce. We benchmark IBM Qiskit Runtime, Q-CTRL Performance Management, and Qedma QESEM on IBM Pittsburgh, a 156-qubit IBM Quantum Heron r3 processor. For Sampler workloads, we run Bernstein-Vazirani, quantum phase estimation, GHZ-state preparation, and randomized mirror circuits with up to 100 measured qubits, comparing raw execution, IBM measurement twirling, and Q-CTRL. For Estimator workloads, we measure chain-averaged magnetization and correlation observables of an eight-layer transverse-field Ising circuit at 25, 50, and 75 qubits against an exact matrix-product-state reference, comparing IBM raw execution, IBM TREX plus twirling, Q-CTRL, and QESEM. Q-CTRL produced the best results on the three structured Sampler workloads while keeping reported QPU times within the same order as the IBM configurations. Across six Ising observable and system-size cases, aggregate mean absolute error was 0.0883 for IBM raw execution, 0.0807 for IBM TREX plus twirling, 0.0285 for Q-CTRL, and 0.0188 for QESEM. Relative to raw execution, Q-CTRL and QESEM reduced aggregate error by factors of 3.10 and 4.70, respectively, while QESEM used 7.5 to 11.1 times the reported QPU time of Q-CTRL. These results show that managed error suppression and mitigation can substantially improve current hardware performance, but with distinct accuracy and execution-time tradeoffs.
Deploying quantum machine learning algorithms on near-term quantum hardware requires circuits that respect device-specific gate sets, connectivity constraints, and noise characteristics. We present a hardware-aware Neural Architecture Search (NAS) approach for designing quantum feature maps that are natively executable on IBM quantum processors without transpilation overhead. Using genetic algorithms to evolve circuit architectures constrained to IBM Torino native gates (ECR, RZ, SX, X), we demonstrate that automated architecture search can discover quantum Support Vector Machine (QSVM) feature maps achieving competitive performance while guaranteeing hardware compatibility. Evaluated on the UCI Breast Cancer Wisconsin dataset, our hardware-aware NAS discovers a 12-gate circuit using exclusively IBM native gates (6 ECR, 3 SX, 3 RZ) that achieves 91.23 % accuracy on 10 qubits-matching unconstrained gate search while requiring zero transpilation. This represents a 27 percentage point improvement over hand-crafted quantum feature maps (64 % accuracy) and approaches the classical RBF SVM baseline (93 %). We show that removing architectural constraints (fixed RZ placement) within hardware-aware search yields 3.5 percentage point gains, and that 100 % native gate usage eliminates decomposition errors that plague universal gate compilations. Our work demonstrates that hardware-aware NAS makes quantum kernel methods practically deployable on current noisy intermediate-scale quantum (NISQ) devices, with circuit architectures ready for immediate execution without modification.