We present noisebridge, an open-source quantum error correction (QEC) SDK implementing a Syndrome Neural Network (SNN) decoder based on a centering-matrix architecture. We report the first published result of zero decoder overhead on real IBM quantum hardware: on IBM Kingston (156-qubit Heron r2 processor, heavy-hex topology), a Z-only rotated surface code of distance d=3 achieves LER_SNN = LER_raw = 0.0422 at p=0.25 — the SNN decoder introduces no additional logical error rate beyond the irreducible hardware noise floor. At p=0.10 the SNN achieves a 1.72x improvement over the standard minimum-weight lookup decoder (LER_SNN=0.0457 vs LER_std=0.0784). A critical architectural insight enables these results: the initial state |0>^9 is not an eigenstate of X-stabilizers, rendering X-syndrome measurement pure noise that inflates circuit depth from 26 to 242 in standard implementations. By restricting to Z-stabilizer measurement only (13 qubits, depth 26, CZ=25, SWAP=0), syndrome accuracy reaches 83.3%, allowing the SNN to bridge the remaining gap to the fault-tolerance threshold. Key results:- Circuit depth: 26 (vs 242 in prior versions, -89%)- Two-qubit gates: CZ=25 (vs CZ=153, -84%)- Z-syndrome accuracy: 83.3% at p=0.10 / 82.5% at p=0.25- LER_SNN = 0.0457 (1.72x over std decoder) at p=0.10- LER_SNN = LER_raw = 0.0422 (zero overhead) at p=0.25- Hardware: IBM Kingston, 13 May 2026 All experiments executed on live IBM hardware. Code available at github.com/noisebridge under MIT license.
We present noisebridge, an open-source quantum error correction (QEC) SDK implementing a Syndrome Neural Network (SNN) decoder based on a centering-matrix architecture. We report the first published result of zero decoder overhead on real IBM quantum hardware: on IBM Kingston (156-qubit Heron r2 processor, heavy-hex topology), a Z-only rotated surface code of distance d=3 achieves LER_SNN = LER_raw = 0.0422 at p=0.25 — the SNN decoder introduces no additional logical error rate beyond the irreducible hardware noise floor. At p=0.10 the SNN achieves a 1.72x improvement over the standard minimum-weight lookup decoder (LER_SNN=0.0457 vs LER_std=0.0784). A critical architectural insight enables these results: the initial state |0>^9 is not an eigenstate of X-stabilizers, rendering X-syndrome measurement pure noise that inflates circuit depth from 26 to 242 in standard implementations. By restricting to Z-stabilizer measurement only (13 qubits, depth 26, CZ=25, SWAP=0), syndrome accuracy reaches 83.3%, allowing the SNN to bridge the remaining gap to the fault-tolerance threshold. Key results:- Circuit depth: 26 (vs 242 in prior versions, -89%)- Two-qubit gates: CZ=25 (vs CZ=153, -84%)- Z-syndrome accuracy: 83.3% at p=0.10 / 82.5% at p=0.25- LER_SNN = 0.0457 (1.72x over std decoder) at p=0.10- LER_SNN = LER_raw = 0.0422 (zero overhead) at p=0.25- Hardware: IBM Kingston, 13 May 2026 All experiments executed on live IBM hardware. Code available at github.com/noisebridge under MIT license.
Syndrome decoding is an integral but computationally demanding step in the implementation of quantum error correction for fault-tolerant quantum computing. Here, we report the development and benchmarking of Artificial Neural Network (ANN) decoding on IBM quantum processors. We demonstrate that ANNs can efficiently decode syndrome measurement data from heavy-hexagonal code architecture and apply appropriate corrections to facilitate error protection. The current physical error rates of IBM devices are above the code's threshold and restrict the scope of our ANN decoder for logical error rate suppression. However, our work confirms the applicability of ANN decoding methods of syndrome data retrieved from experimental devices and establishes machine learning as a promising pathway for quantum error correction when quantum devices with below threshold error rates become available in the near future. Published by the American Physical Society 2024
Quantum computers can solve selected problems more efficiently than classical computers, but current devices are limited by high physical error rates. Quantum Error Correction (QEC) mitigates this by encoding many physical qubits into a logical qubit, with the surface code among the most widely studied approaches. Since syndrome measurements are produced continuously, the decoder must process them fast enough to avoid becoming a system bottleneck, making real-time decoding essential for fault-tolerant quantum computing. While most state-of-the-art real-time decoders rely on Minimum-Weight Perfect Matching (MWPM), we instead use a high-accuracy Graph Neural Network (GNN) that trades higher computational cost for lower logical error rates. To make this GNN practical for real-time decoding, we apply algorithm-hardware co-design. We reduce complexity through hardware-guided pruning and retraining, producing two hardware-friendly models that reduce parameter count by 3.1× and 6.5×. These target, respectively, an average decoding latency of one syndrome cycle and a worst-case latency within one syndrome cycle. We further reduce hardware cost using input-graph filtering and post-training quantization. Based on these optimized models, we propose an FPGA-based architecture for low-latency inference and real-time decoding. Evaluated on surface codes up to distance 7 under circuit-level noise at physical error rate p=10−3, our decoder outperforms MWPM in decoding accuracy for both average-latency and max-latency settings. It reduces logical error rate by 40% at 1μs average latency, and by 13% under a strict 1μs deadline.
We apply the inZOR-ND bio-adaptive genomic discovery engine to quantum error correction (QEC) on real IBM Quantum hardware, without implementing any known QEC code structure. Two versions are presented: v1 (21 Ry parameters, X-only correction with 8 syndromes, 4 test states) and v2 (42 Ry+Rz parameters, Full Pauli correction with 22 syndromes, 6 test states, multi-noise training over 4 CZ error rate levels). Both versions discover hardware-native 7-qubit encoding circuits optimized for the IBM Heron processor's tree topology (ibm_fez physical qubits 3, 2, 4, 16, 1, 5, 23). Across 7 hardware runs on ibm_fez and ibm_marrakesh, inZOR-ND outperforms Steane [[7,1,3]] in all observed hardware runs, with gains from +0.2 to +5.1 percentage points. The key finding is not that inZOR-ND produces a theoretically superior code — in ideal depolarizing noise simulation, Steane's Full Pauli correction remains stronger at all tested noise levels. Rather, these results suggest that genomic search can discover hardware-native QEC encoders whose reduced transpiled cost yields consistent advantage over theoretically stronger but hardware-mismatched codes on NISQ devices. This demonstrates that theoretical optimality is not the same as hardware optimality on current processors. The core hardware advantage: inZOR-ND's native CZ circuits transpile to depth ~53–58 on IBM Heron, while the Steane code (CNOT-based) transpiles to ~115, because CZ is a native IBM Heron gate while CNOT requires decomposition. v2 Rz gates are virtual (zero depth, zero error) on Heron. v1 LUPA precision zoom: simulation fidelity 0.999843 (p_cz=0.002, X-only, 3 rounds × 20 cycles, ~5 min). v2 Qiskit AerSimulator cross-validation: perfect match with NumPy simulator (diff < 1e-16). Key results: - inZOR-ND outperforms Steane in 7/7 observed hardware runs - v1 sim fidelity (LUPA): 0.999843 - v2 sim fidelity (multi-noise avg, Full Pauli): 0.990244 - Best hardware gain vs Steane: +5.1 pp (ibm_marrakesh, noisy regime) - v1 transpiled depth: ~53 | v2: ~58 | Steane: ~115 (IBM Heron) - v1: 21 params (Ry) | v2: 42 params (Ry+Rz) | 12 CZ gates - v2 syndromes: 22 (Full Pauli: I + 7X + 7Y + 7Z) - 8000 shots per circuit, SamplerV2 runtime API
Real-time decoding of quantum error correction (QEC) is essential for enabling fault-tolerant quantum computation. A practical decoder must operate with high accuracy at low latency, while remaining robust to spatial and temporal variations in hardware noise. We introduce a hardware-conditioned neural decoder framework designed to exploit the natural separation of timescales in superconducting processors, where calibration drifts occur over hours while error correction requires microsecond-scale responses. By processing calibration data through a graph-based encoder and conditioning a lightweight convolutional backbone via feature-wise linear modulation (FiLM), we decouple the heavy processing of device statistics from the low-latency syndrome decoding.
We evaluate this approach using the 1D repetition code as a testbed on IBM Fez, Kingston, and Pittsburgh processors, collecting over 2.7 million experimental shots spanning distances up to d = 11. We demonstrate that a single trained model generalizes to unseen qubit chains and new calibration data acquired days later without retraining. On these unseen experiments, the FiLM-conditioned decoder achieves up to an 11.1x reduction in logical error rate relative to modified minimum-weight perfect matching. We observe that by employing a network architecture that exploits the highly asynchronous nature of system calibration and decoding, hardware-conditioned neural decoding demonstrates promising, adaptive performance with negligible latency overhead relative to unconditioned baselines.
Fault-tolerant quantum computing with the surface code requires a classical decoder that returns a correction in less than one syndrome extraction round-a latency budget of approximately 1 us on superconducting hardware that is below what software decoders achieve and at the edge of what FPGA and GPU implementations report. We present tt-qec-predecoder, an end-to-end pre-decoder system targeting this regime by mapping a selective-scan state-space model (Mamba/S6) onto the Tenstorrent Blackhole RISC-V tensor architecture, combined with a hardware-resident integrity and formal-verification pipeline. The decoder is a 16 M-parameter Sparse Mamba network whose recurrence has O(k) work in k, the number of non-trivial syndrome bits, executed as a tile-resident Tensix kernel with no host round-trip. Around the kernel we build a Z3-based proof framework that discharges five abstract safety obligations (no NoC deadlock, no buffer overflow, worst-case latency bound, fixed-point quantizer error bound, no-op safety), a BLAKE3 content-addressed integrity chain (QCIVET) covering every artifact from training data to deployed weights, and a standardized benchmarking suite (qec-lego-bench) for like-for-like comparison against PyMatching (CPU), Micro Blossom (FPGA), and NVIDIA Ising (GPU) baselines at code distances d = {3,5,7,9, 13, 17, 21, 25, 32}. We describe the architecture, the kernel design and its hardware-aware Taylor-approximated discretization, the verification methodology and its current limitations, and the benchmarking framework. We additionally report a first round of experimental validation: measured CPU baselines on the FP32 dense reference model, Blackhole latencies projected from those baselines through a published scaling chain (INT4 quantization, tensor-core SIMD, Tenstorrent NoC streaming), an end-to-end decode run on the IBM Quantum cloud simulator, and as a new empirical result-50,000 shots of raw complex-valued IQ syndrome data harvested from a real IBM Heron R2 processor (ibm_fez) via the IBM Quantum open plan. Real-hardware Blackhole validation remains explicitly pending.
Real-time decoding is a major bottleneck in scaling quantum error correction (QEC) from noisy intermediate-scale quantum (NISQ) devices to fault-tolerant quantum computing. We present an adaptive confidence-gated decoding framework for the rotated surface code that treats decoding as a two-stage inference problem. A lightweight feed-forward neural network performs fast-path decoding for the majority of syndrome measurements, while only low-confidence predictions are escalated to a minimum-weight perfect matching (MWPM) refinement stage. We benchmark the framework on rotated surface codes with distances d∈{3,5,7,9,11} under circuit-level depolarising noise using the Stim stabiliser simulator. The evaluation characterises logical accuracy, confidence-controlled accuracy-latency trade-offs, decoding throughput, per-shot latency, and decoding-graph resource scaling. Routing only 3.3%-6.2% of syndromes to the refinement stage improves logical accuracy from 99.21% for the neural-only baseline to 99.81% at a confidence threshold of 0.95 while incurring only a bounded increase in average decoding cost. Neural-decoder throughput saturates near 4.6×105 samples s−1 at batch size 512 on commodity CPU hardware, indicating that the neural fast path is not the dominant throughput bottleneck beyond code distance d=7. We release the complete benchmarking pipeline, trained models, raw benchmark data, and source code, and explicitly distinguish the experimentally validated contributions from the broader hardware-aware QEC co-design roadmap, including hardware-constrained code discovery, GPU-accelerated inference, and multi-noise optimisation, which remain directions for future work.