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Governed Fault-Tolerant Quantum Computing on Commodity NISQ Hardware: Surface-Code QEC, Universal FTQC Primitives, FTQC Composition, and Chemical Accuracy FTQC across H2, LiH, H2O, BeH2 Ground States, and the BeH2 Strongly-Multireference Transition State on the IBM Heron r2 and r3 Families of QPUs

Denise Holt, Denis Ovseyenko

Published Jun 7, 2026• 4 citations
Publisher

Abstract

Abstract This paper reports the first end-to-end fault-tolerant quantum computing stack to clear all four strict-FTQC requirements simultaneously on commodity superconducting NISQ silicon, rented through standard IBM Quantum cloud subscription with no purpose-built research machine, no custom decoder, and no magic-state distillation factory. The four requirements: (i) surface-code quantum error correction at distance d≥3 with logical-error rate below the unencoded baseline; (ii) a universal Clifford+T gate set executed via magic-state injection, with no arbitrary angle physical rotation carrying non-Clifford content on the wire (the algorithm-determined non-Clifford angle never fires on the silicon; the native RZ(θphys) on Heron fires only at Clifford-multiple angles required to compose H, S, T); (iii) heterogeneous primitive composition (teleportation, lattice-surgery CNOT, T-gate, logical memory) on a persistent encoded register; and (iv) runtime admissibility verification on every committed result. All five chips, five chemistry workloads spanning four molecules, and twenty-two governed runs in this paper were executed on the same primitive engine without architectural change. The architectural shift that makes this work on today’s hardware is the d=1 inversion: a 150-qubit governed encoded register held at substrate distance d=1 on the chip’s physical qubits, with logical fidelity preserved by Seed IQ execution governance over the encoded layer rather than by a larger code distance. Where the standard surface-code paradigm grows physical d quadratically to drive the logical-error rate down—and pays for it with magic-state fidelity that degrades as gate depth scales—Seed IQ governance acts as an operational substitute for code distance: it delivers the equivalent error-rate reduction in software while leaving the per-gate channel fidelity available for T-gate injection and Clifford operations intact. The result: the four strict-FTQC requirements hold simultaneously at approximately one physical qubit per logical qubit, against the ∼ 625 physical qubits per logical qubit required by the IBM 2029 roadmap target of d=25 surface code at comparable logical fidelity. Seed IQ is an Active Inference and Adaptive Multiagent Autonomous Control (AMAC) platform from AIX Global Innovations. Campaign summary. Eight stages, April through June 2026, across five IBM Heron processors (r2: IBM Fez, IBM Kingston, IBM Marrakesh, IBM Pittsburgh; r3: IBM Boston). April 9 — surface-code QEC: −88.5% LER reduction at d=3 on IBM Fez, −93.1% at d=5 where the MWPM+UF baseline collapsed, −60.9% at d=3 on 1.28°ø dirtier IBM Pittsburgh silicon. April 23–25 — all four universal FTQC primitives cleared the classical 2/3 entanglement bound at F≈0.99. April 25–26 — heterogeneous TELE→CNOT→T→CNOT→TELE°ø2 composition: 22,500 circuits at Fgoverned=1.0000, zero detected logical errors. May 7–9 — H2, 10 runs across 3 chips, 10/10 inside chem-acc, best ΔE=+0.0157mHa, two chips bit-identical to twelve decimals. May 23 —LiH, 3 runs across 3 chips, 3/3 inside chem-acc, two chips tied at ΔE=+0.056mHa. May 28–30 — H2O, 3 runs across 3 chips, 3/3 inside chem-acc at ΔE=+0.051mHa, all three bit-identical to twelve decimals. May 30–31 — BeH2 equilibrium, 3 runs across 2 chips, 3/3 inside chem-acc at ΔE=+0.000595mHa (2690.9°ø inside, the only sub-wavenumber QPU chemistry commit on record), all three bit-identical to twelve decimals. June 1 — BeH2 transition state (|cHF |2≈0.5 strong multireference, the canonical territory where single-reference CCSD breaks), 3 runs across two Heron processor generations at two Newton optimization depths on the rank-5 C2v trial-state subspace, 3/3 inside chem-acc on a 62-Pauli-term Hamiltonian; the two 2-D Newton runs (IBM Boston Heron r3, IBM Kingston Heron r2) commit bit-identical to twelve decimals at ΔE=+0.018189mHa, and the 4-D Newton run commits at the deeper fixed point at ΔE=+0.012643mHa (126.6°ø inside chem-acc, 1.6°ø inside the CCSD(T) gold band). Aggregate: twenty-two runs, 22/22 inside chemical accuracy. No prior NISQ-chemistry or partial-FTQC-chemistry result on commodity hardware has cleared this combination of accuracy and cross-chip reproducibility. Full per-stage detail in Åò4–Åò12.8. Compliance. All twenty-two committed chemistry runs and every primitive composition stage passed the four-requirement FTQC compliance check: closed Clifford+T compilation, magicstate-injected T-gates, encoded-register fidelity preservation, runtime admissibility verification. Fgoverned=1.0000 is the runtime admissibility pass-rate—every committed primitive cleared every admissibility check across the composition pipeline (22,500 composed circuits per run, replicated across two independent calibration windows for 45,000 circuits total) and the twenty-two chemistry runs, with zero detected logical errors, computed from per-shot stabilizer-syndrome statistics, entanglement-witness measurements, and the three-stage admissibility check under live IBM Heron hardware noise (Åò7, Åò13.13). The twelve-decimal cross-chip identity is the engineered signature of Seed IQ’s admissibility-and-projection contract: the three-stage envelope is designed so that noisy QPU measurement vectors from materially different chips identify the same Newton fixed point on the trial-state subspace; the committed energy is then the Hamiltonian sum E=Pi ci⟨Pi⟩ at that shared fixed point evaluated directly from each chip’s own QPU shot record by direct bitstring counting at the continuous coordinate—no binning, no precomputed energy curve, no offline lookup. IEEE 754 doubles are just the number format the energies are reported in; what makes the twelve decimal places physically meaningful is that materially different chips, with materially different noise, agree at all twelve. That agreement is the operational evidence the envelope is delivering what it was engineered to: an admissibility-and-projection contract that maps independent noisy QPU measurement vectors to the same fixed point on the trial-state subspace (Åò13.10, Åò14).

DOI
10.5281/zenodo.20585364

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Demonstrating Exact Financial Risk Calculations on NISQ Quantum Hardware with Precision No Sampling Method Can Reach - Governed Fault-Tolerant Quantum Computation under Seed IQ on the Superconducting IBM Heron r2/r3 QPUs—Beating the NVIDIA STAC-A2 GPU Risk Record Without Sampling

Denise Holt, Denis Ovseyenko

Abstract We demonstrate governed fault-tolerant quantum computing (GFTQC) applied to financial risk: every number is computed exactly, with a precision and reproducibility no sampling method can reach. Every risk number a financial institution must produce, a value-at-risk, an expected shortfall, a valuation adjustment, and the price and Greeks beneath them, is at bottom an expectation: a probability-weighted integral of a payoff over the distribution of future market paths. The industry evaluates these integrals by Monte-Carlo sampling, and sampling has two structural defects. Its statistical error falls only as 1/√N in the number of paths, so each additional digit costs a hundredfold more compute; and the estimate drifts from one run to the next, so it cannot deliver the auditable, reproducible numbers the FRTB P&L Attribution (PLA) test demands. The industry’s response has been to sample faster: NVIDIA’s audited STAC-A2 record [26], the benchmark for derivatives-risk computation, runs 561 option-valuations per second on an 8×H100 GPU server over 316 million paths, which is faster sampling and still stochastic. The quantum proposals do not close the gap either: the near-term methods (VQE, QAOA, QPE) only estimate, and the machines that would carry the field past sampling are a 2030+ prospect, not today. The field, in short, is caught between classical sampling that never becomes exact (Monte Carlo, quasi-Monte Carlo, GPU-accelerated) and quantum methods that either only estimate today (VQE, QPE, QAOA) or await a 2030+ roadmap. Governed fault-tolerant quantum computing (GFTQC) sits in neither camp: it commits the exact value on hardware that exists now. We compute the risk on quantum hardware that exists now, and we compute it exactly and deterministically. Under Seed IQ, a fault-tolerant quantum computation on the 156-qubit IBM Heron QPU encodes the risk-neutral density as a governed quantum register and computes its expectation at a self-certified eigenstate, rather than estimating it from repeated measurement. This is the same governed determinism our companion fault-tolerant quantum work established on the very same hardware—FCI-exact hydrogen-chain energies committed on IBM Boston (Heron r3), internally certified exact and reproducible to twelve decimal places [1, 2]; here that deterministic, on-hardware exactness is turned on the derivatives integral. The dissipative dynamics converge to the target eigenstate and the output is exact to machine precision, with zero variance and byte-identical on rerun—the 10−12 price no sampler reaches at any budget, delivered directly. Across structured products, factor-model risk, XVA and expected shortfall the story is the same: exact where Monte Carlo is noisy, reproducible where it drifts. That the same exact computation is also 35× faster than NVIDIA’s eight-GPU record on the audited STAC-A2 workload is a consequence of not sampling, not the headline; the headline is that the number is right to the last digit. The gap is not incremental. What separates this work from the standard quantum-finance roadmap is not a constant factor but the machine itself (Fig. 2): textbook fault-tolerant pricing needs a computer of 10^6–10^9 physical qubits with distillation factories, projected for the 2030s; GFTQC commits the same exact, fault-tolerant risk numbers today on a 156-qubit superconducting IBM Heron QPU, a ∼10^6× smaller physical footprint. Exact, reproducible, auditable financial risk is available now, not next decade.

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Magic state distillation is a key component of fault-tolerant quantum computation, as it enables the implementation of non-Clifford gates such as the $T$ gate and the $CCZ$ gate via gate teleportation. However, conventional distillation protocols require a large number of logical qubits and introduce substantial spatial and temporal overhead, posing a significant bottleneck for scalable fault-tolerant quantum computation. In this work, we propose a zero-level distillation protocol that efficiently generates a high-fidelity logical $CCZ$ magic state using only physical qubits on a two-dimensional square lattice with nearest-neighbor interactions. Our method leverages the transversal $T/T^\dagger$ operation of the $[[ 8,3,2 ]]$ code to fault-tolerantly encode the state $\overline{CCZ}|+++\rangle$, which is subsequently teleported to three surface-code logical qubits via lattice surgery. To enable teleportation between codes with different distances, we introduce adaptively initialized teleportation (AIT), a tailored initialization procedure for the surface code. Numerical simulations demonstrate that the logical error rate scales as $p_L \simeq 300 \times p^2$ with respect to the physical error rate $p$. For example, the proposed method improves the logical error rate by approximately one and two orders of magnitude at $p = 10^{-3}$ and $p = 10^{-4}$, respectively, compared to conventional seven-$T$-gate approaches. The distillation circuit requires only 22 physical qubits, 3 logical qubits, and a circuit depth of 24, reducing the space-time overhead by a factor of approximately 5-10 compared to previous methods. This result highlights the practicality of $CCZ$-state distillation in early fault-tolerant quantum computation and offers a new direction toward resource-efficient physical-level magic state distillation beyond conventional $T$-state generation.

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As the quantum computing field transitions toward Fault-Tolerant Quantum Computing (FTQC), intensive efforts are focused on scaling architectures and realizing active error correction. However, this shift introduces security surfaces that remain largely unexplored. Fault-tolerant quantum computers pair a quantum processor with a classical decoder that sits on the critical path of every syndrome-extraction round. For the first time, this work demonstrates that the wall-clock time each decoder takes to process a syndrome measurement and decoding round constitutes a novel, exploitable hardware side channel on physical quantum hardware. Using per-shot decoder timings from three IBM Heron processors collected over a 68-day window, the decode-time distribution alone allows a passive observer to (i) reconstruct the shot-by-shot detector-firing distribution and estimate the workload's logical error rate $p_L$, (ii) infer the code distance in use, and (iii) fingerprint the specific physical device with up to 89% accuracy (a random guess is 33%), with a pooled two-sample Kolmogorov-Smirnov test confirming the decode-time distributions are statistically distinct. In noisy simulation inspired by public data from Google's 105-qubit Willow processor, decoder timing further distinguishes 9 surface-code patches at different locations on the chip with 81% accuracy, showing the side channel persists on below-threshold fault-tolerant hardware from a different vendor and code family.

arXiv:2609.12145•Sep 10, 2026•0 citations
Abstract This paper reports the first end-to-end fault-tolerant quantum computing stack to clear all four strict-FTQC requirements simultaneously on commodity superconducting NISQ silicon, rented through standard IBM Quantum cloud subscription with no purpose-built research machine, no custom decoder, and no magic-state distillation factory. The four requirements: (i) surface-code quantum error correction at distance d≥3 with logical-error rate below the unencoded baseline; (ii) a universal Clifford+T gate set executed via magic-state injection, with no arbitrary angle physical rotation carrying non-Clifford content on the wire (the algorithm-determined non-Clifford angle never fires on the silicon; the native RZ(θphys) on Heron fires only at Clifford-multiple angles required to compose H, S, T); (iii) heterogeneous primitive composition (teleportation, lattice-surgery CNOT, T-gate, logical memory) on a persistent encoded register; and (iv) runtime admissibility verification on every committed result. All five chips, five chemistry workloads spanning four molecules, and twenty-two governed runs in this paper were executed on the same primitive engine without architectural change. The architectural shift that makes this work on today’s hardware is the d=1 inversion: a 150-qubit governed encoded register held at substrate distance d=1 on the chip’s physical qubits, with logical fidelity preserved by Seed IQ execution governance over the encoded layer rather than by a larger code distance. Where the standard surface-code paradigm grows physical d quadratically to drive the logical-error rate down—and pays for it with magic-state fidelity that degrades as gate depth scales—Seed IQ governance acts as an operational substitute for code distance: it delivers the equivalent error-rate reduction in software while leaving the per-gate channel fidelity available for T-gate injection and Clifford operations intact. The result: the four strict-FTQC requirements hold simultaneously at approximately one physical qubit per logical qubit, against the ∼ 625 physical qubits per logical qubit required by the IBM 2029 roadmap target of d=25 surface code at comparable logical fidelity. Seed IQ is an Active Inference and Adaptive Multiagent Autonomous Control (AMAC) platform from AIX Global Innovations. Campaign summary. Eight stages, April through June 2026, across five IBM Heron processors (r2: IBM Fez, IBM Kingston, IBM Marrakesh, IBM Pittsburgh; r3: IBM Boston). April 9 — surface-code QEC: −88.5% LER reduction at d=3 on IBM Fez, −93.1% at d=5 where the MWPM+UF baseline collapsed, −60.9% at d=3 on 1.28°ø dirtier IBM Pittsburgh silicon. April 23–25 — all four universal FTQC primitives cleared the classical 2/3 entanglement bound at F≈0.99. April 25–26 — heterogeneous TELE→CNOT→T→CNOT→TELE°ø2 composition: 22,500 circuits at Fgoverned=1.0000, zero detected logical errors. May 7–9 — H2, 10 runs across 3 chips, 10/10 inside chem-acc, best ΔE=+0.0157mHa, two chips bit-identical to twelve decimals. May 23 —LiH, 3 runs across 3 chips, 3/3 inside chem-acc, two chips tied at ΔE=+0.056mHa. May 28–30 — H2O, 3 runs across 3 chips, 3/3 inside chem-acc at ΔE=+0.051mHa, all three bit-identical to twelve decimals. May 30–31 — BeH2 equilibrium, 3 runs across 2 chips, 3/3 inside chem-acc at ΔE=+0.000595mHa (2690.9°ø inside, the only sub-wavenumber QPU chemistry commit on record), all three bit-identical to twelve decimals. June 1 — BeH2 transition state (|cHF |2≈0.5 strong multireference, the canonical territory where single-reference CCSD breaks), 3 runs across two Heron processor generations at two Newton optimization depths on the rank-5 C2v trial-state subspace, 3/3 inside chem-acc on a 62-Pauli-term Hamiltonian; the two 2-D Newton runs (IBM Boston Heron r3, IBM Kingston Heron r2) commit bit-identical to twelve decimals at ΔE=+0.018189mHa, and the 4-D Newton run commits at the deeper fixed point at ΔE=+0.012643mHa (126.6°ø inside chem-acc, 1.6°ø inside the CCSD(T) gold band). Aggregate: twenty-two runs, 22/22 inside chemical accuracy. No prior NISQ-chemistry or partial-FTQC-chemistry result on commodity hardware has cleared this combination of accuracy and cross-chip reproducibility. Full per-stage detail in Åò4–Åò12.8. Compliance. All twenty-two committed chemistry runs and every primitive composition stage passed the four-requirement FTQC compliance check: closed Clifford+T compilation, magicstate-injected T-gates, encoded-register fidelity preservation, runtime admissibility verification. Fgoverned=1.0000 is the runtime admissibility pass-rate—every committed primitive cleared every admissibility check across the composition pipeline (22,500 composed circuits per run, replicated across two independent calibration windows for 45,000 circuits total) and the twenty-two chemistry runs, with zero detected logical errors, computed from per-shot stabilizer-syndrome statistics, entanglement-witness measurements, and the three-stage admissibility check under live IBM Heron hardware noise (Åò7, Åò13.13). The twelve-decimal cross-chip identity is the engineered signature of Seed IQ’s admissibility-and-projection contract: the three-stage envelope is designed so that noisy QPU measurement vectors from materially different chips identify the same Newton fixed point on the trial-state subspace; the committed energy is then the Hamiltonian sum E=Pi ci⟨Pi⟩ at that shared fixed point evaluated directly from each chip’s own QPU shot record by direct bitstring counting at the continuous coordinate—no binning, no precomputed energy curve, no offline lookup. IEEE 754 doubles are just the number format the energies are reported in; what makes the twelve decimal places physically meaningful is that materially different chips, with materially different noise, agree at all twelve. That agreement is the operational evidence the envelope is delivering what it was engineered to: an admissibility-and-projection contract that maps independent noisy QPU measurement vectors to the same fixed point on the trial-state subspace (Åò13.10, Åò14).
Abstract We demonstrate governed fault-tolerant quantum computing (GFTQC) applied to financial risk: every number is computed exactly, with a precision and reproducibility no sampling method can reach. Every risk number a financial institution must produce, a value-at-risk, an expected shortfall, a valuation adjustment, and the price and Greeks beneath them, is at bottom an expectation: a probability-weighted integral of a payoff over the distribution of future market paths. The industry evaluates these integrals by Monte-Carlo sampling, and sampling has two structural defects. Its statistical error falls only as 1/√N in the number of paths, so each additional digit costs a hundredfold more compute; and the estimate drifts from one run to the next, so it cannot deliver the auditable, reproducible numbers the FRTB P&L Attribution (PLA) test demands. The industry’s response has been to sample faster: NVIDIA’s audited STAC-A2 record [26], the benchmark for derivatives-risk computation, runs 561 option-valuations per second on an 8×H100 GPU server over 316 million paths, which is faster sampling and still stochastic. The quantum proposals do not close the gap either: the near-term methods (VQE, QAOA, QPE) only estimate, and the machines that would carry the field past sampling are a 2030+ prospect, not today. The field, in short, is caught between classical sampling that never becomes exact (Monte Carlo, quasi-Monte Carlo, GPU-accelerated) and quantum methods that either only estimate today (VQE, QPE, QAOA) or await a 2030+ roadmap. Governed fault-tolerant quantum computing (GFTQC) sits in neither camp: it commits the exact value on hardware that exists now. We compute the risk on quantum hardware that exists now, and we compute it exactly and deterministically. Under Seed IQ, a fault-tolerant quantum computation on the 156-qubit IBM Heron QPU encodes the risk-neutral density as a governed quantum register and computes its expectation at a self-certified eigenstate, rather than estimating it from repeated measurement. This is the same governed determinism our companion fault-tolerant quantum work established on the very same hardware—FCI-exact hydrogen-chain energies committed on IBM Boston (Heron r3), internally certified exact and reproducible to twelve decimal places [1, 2]; here that deterministic, on-hardware exactness is turned on the derivatives integral. The dissipative dynamics converge to the target eigenstate and the output is exact to machine precision, with zero variance and byte-identical on rerun—the 10−12 price no sampler reaches at any budget, delivered directly. Across structured products, factor-model risk, XVA and expected shortfall the story is the same: exact where Monte Carlo is noisy, reproducible where it drifts. That the same exact computation is also 35× faster than NVIDIA’s eight-GPU record on the audited STAC-A2 workload is a consequence of not sampling, not the headline; the headline is that the number is right to the last digit. The gap is not incremental. What separates this work from the standard quantum-finance roadmap is not a constant factor but the machine itself (Fig. 2): textbook fault-tolerant pricing needs a computer of 10^6–10^9 physical qubits with distillation factories, projected for the 2030s; GFTQC commits the same exact, fault-tolerant risk numbers today on a 156-qubit superconducting IBM Heron QPU, a ∼10^6× smaller physical footprint. Exact, reproducible, auditable financial risk is available now, not next decade.
Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding. This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.
Fault-tolerant quantum computing (FTQC) is required to execute quantum algorithms capable of tackling computationally intractable problems in chemistry, material science, and cryptography. Noisy Intermediate-Scale Quantum (NISQ) devices remain constrained by physical error rates that degrade quantum coherence over short circuit depths. Quantum error correction (QEC) protects fragile logical states by encoding them into non-local degrees of freedom across topological physical qubit arrays. This research presents a comprehensive architectural and theoretical evaluation of three primary QEC paradigms: planar surface codes, topological color codes, and asymptotic quantum low-density parity-check (qLDPC) codes. We examine error thresholds, transversal gate constraints governed by the Eastin-Knill theorem, magic state distillation (MSD) overheads, lattice surgery, and classical decoding latencies across superconducting transmons, trapped ions, and neutral atom platforms.
Quantum error correction (QEC) is beginning to enable logical operations that outperform their unencoded physical counterparts, but useful fault-tolerant computation will require more than low-error quantum memory. An effective architecture must orchestrate efficient logical encoding, low-overhead logical operations, and access to the non-Clifford resources required for universal computation. Here, we introduce and experimentally validate such an architecture based on the [[20,2,6]][[20,2,6]][[20,2,6]] C4C_4C4​-Helix code, designed for the early fault-tolerant regime. Using Quantinuum Helios, a 98-qubit trapped-ion quantum processor, we experimentally demonstrate the principal components of this architecture: we perform repeated quantum error correction with an error of 4.6−2.6+6.2×10−54.6^{+6.2}_{-2.6}\times10^{-5}4.6−2.6+6.2​×10−5 per logical qubit per QEC cycle. We benchmark the complete Clifford group on the two logical qubits of a single codeblock under active error correction, obtaining an error of 2.8−1.6+1.0×10−42.8^{+1.0}_{-1.6}\times 10^{-4}2.8−1.6+1.0​×10−4 per two-qubit logical Clifford. We further demonstrate a fault-tolerant chain-map interface between C4C_4C4​-Helix and a distance-5 surface code, preparing a heterogeneous three-logical-qubit GHZ state with a fidelity lower bound of 99.925−0.245+0.068%99.925^{+0.068}_{-0.245}\%99.925−0.245+0.068​%. In each case, the encoded implementation outperforms its corresponding unencoded physical baseline without relying on postselection. Circuit-level simulations indicate that improvements in physical fidelity bring the same architecture into the 10−610^{-6}10−6-10−810^{-8}10−8 logical-error regime targeted for early fault-tolerant computation. Together, these results establish C4C_4C4​-Helix as a hardware-validated fault-tolerant architecture rather than a bare quantum memory.
Zero-level CCZCCZCCZ Distillation
Magic state distillation is a key component of fault-tolerant quantum computation, as it enables the implementation of non-Clifford gates such as the TTT gate and the CCZCCZCCZ gate via gate teleportation. However, conventional distillation protocols require a large number of logical qubits and introduce substantial spatial and temporal overhead, posing a significant bottleneck for scalable fault-tolerant quantum computation. In this work, we propose a zero-level distillation protocol that efficiently generates a high-fidelity logical CCZCCZCCZ magic state using only physical qubits on a two-dimensional square lattice with nearest-neighbor interactions. Our method leverages the transversal T/T†T/T^\daggerT/T† operation of the [[8,3,2]][[ 8,3,2 ]][[8,3,2]] code to fault-tolerantly encode the state CCZ‾∣+++⟩\overline{CCZ}|+++\rangleCCZ∣+++⟩, which is subsequently teleported to three surface-code logical qubits via lattice surgery. To enable teleportation between codes with different distances, we introduce adaptively initialized teleportation (AIT), a tailored initialization procedure for the surface code. Numerical simulations demonstrate that the logical error rate scales as pL≃300×p2p_L \simeq 300 \times p^2pL​≃300×p2 with respect to the physical error rate ppp. For example, the proposed method improves the logical error rate by approximately one and two orders of magnitude at p=10−3p = 10^{-3}p=10−3 and p=10−4p = 10^{-4}p=10−4, respectively, compared to conventional seven-TTT-gate approaches. The distillation circuit requires only 22 physical qubits, 3 logical qubits, and a circuit depth of 24, reducing the space-time overhead by a factor of approximately 5-10 compared to previous methods. This result highlights the practicality of CCZCCZCCZ-state distillation in early fault-tolerant quantum computation and offers a new direction toward resource-efficient physical-level magic state distillation beyond conventional TTT-state generation.
As the quantum computing field transitions toward Fault-Tolerant Quantum Computing (FTQC), intensive efforts are focused on scaling architectures and realizing active error correction. However, this shift introduces security surfaces that remain largely unexplored. Fault-tolerant quantum computers pair a quantum processor with a classical decoder that sits on the critical path of every syndrome-extraction round. For the first time, this work demonstrates that the wall-clock time each decoder takes to process a syndrome measurement and decoding round constitutes a novel, exploitable hardware side channel on physical quantum hardware. Using per-shot decoder timings from three IBM Heron processors collected over a 68-day window, the decode-time distribution alone allows a passive observer to (i) reconstruct the shot-by-shot detector-firing distribution and estimate the workload's logical error rate pLp_LpL​, (ii) infer the code distance in use, and (iii) fingerprint the specific physical device with up to 89% accuracy (a random guess is 33%), with a pooled two-sample Kolmogorov-Smirnov test confirming the decode-time distributions are statistically distinct. In noisy simulation inspired by public data from Google's 105-qubit Willow processor, decoder timing further distinguishes 9 surface-code patches at different locations on the chip with 81% accuracy, showing the side channel persists on below-threshold fault-tolerant hardware from a different vendor and code family.