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arXiv:2609.12145

Hardware Fingerprinting FTQC via Quantum Decoder Timing

Friedrich Doku, Jakub M. Szefer, Kaitlin N. Smith

Published Sep 10, 2026• 0 citations
arXivHTMLPDF

Abstract

As the quantum computing field transitions toward Fault-Tolerant Quantum Computing (FTQC), intensive efforts are focused on scaling architectures and realizing active error correction. However, this shift introduces security surfaces that remain largely unexplored. Fault-tolerant quantum computers pair a quantum processor with a classical decoder that sits on the critical path of every syndrome-extraction round. For the first time, this work demonstrates that the wall-clock time each decoder takes to process a syndrome measurement and decoding round constitutes a novel, exploitable hardware side channel on physical quantum hardware. Using per-shot decoder timings from three IBM Heron processors collected over a 68-day window, the decode-time distribution alone allows a passive observer to (i) reconstruct the shot-by-shot detector-firing distribution and estimate the workload's logical error rate $p_L$, (ii) infer the code distance in use, and (iii) fingerprint the specific physical device with up to 89% accuracy (a random guess is 33%), with a pooled two-sample Kolmogorov-Smirnov test confirming the decode-time distributions are statistically distinct. In noisy simulation inspired by public data from Google's 105-qubit Willow processor, decoder timing further distinguishes 9 surface-code patches at different locations on the chip with 81% accuracy, showing the side channel persists on below-threshold fault-tolerant hardware from a different vendor and code family.

DOI
10.48550/arxiv.2609.12145

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IEEE International Symposium on High-Performance Computer Architecture (HPCA)•Jan 31, 2026•1 citation

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Quantum error correction (QEC) is transitioning from physical feasibility demonstrations to systems engineering challenges. Google has achieved below-threshold performance on distance-5/7 surface codes, while Riverlane and Rigetti have demonstrated hardware-integrated low-latency feedback loops. These milestones indicate that the core challenge of real-time decoding has shifted from algorithmic capability to system-level engineering. However, a substantial engineering gap remains between laboratory demonstrations and scalable fault-tolerant quantum computing (FTQC). This white paper addresses three questions: (1) Where are the real bottlenecks in real-time QEC: beyond average decoder speed, the constraints lie in QEC round time, tail latency, and end-to-end data path coordination; (2) How mature are mainstream decoder algorithms: we benchmark the major decoders for both surface codes and quantum low-density parity-check (qLDPC) codes, evaluating their real-time readiness; (3) What system stack do we propose: a six-layer reference architecture from syndrome acquisition to logical operations, with interface definitions and latency budget models. Our results quantify the gap between current decoder performance and real-time requirements, and identify the architectural choices needed to close it.

quant-pharXiv:2605.30765•Jun 1, 2026•0 citations
As the quantum computing field transitions toward Fault-Tolerant Quantum Computing (FTQC), intensive efforts are focused on scaling architectures and realizing active error correction. However, this shift introduces security surfaces that remain largely unexplored. Fault-tolerant quantum computers pair a quantum processor with a classical decoder that sits on the critical path of every syndrome-extraction round. For the first time, this work demonstrates that the wall-clock time each decoder takes to process a syndrome measurement and decoding round constitutes a novel, exploitable hardware side channel on physical quantum hardware. Using per-shot decoder timings from three IBM Heron processors collected over a 68-day window, the decode-time distribution alone allows a passive observer to (i) reconstruct the shot-by-shot detector-firing distribution and estimate the workload's logical error rate pLp_LpL​, (ii) infer the code distance in use, and (iii) fingerprint the specific physical device with up to 89% accuracy (a random guess is 33%), with a pooled two-sample Kolmogorov-Smirnov test confirming the decode-time distributions are statistically distinct. In noisy simulation inspired by public data from Google's 105-qubit Willow processor, decoder timing further distinguishes 9 surface-code patches at different locations on the chip with 81% accuracy, showing the side channel persists on below-threshold fault-tolerant hardware from a different vendor and code family.
As quantum computing emerges as an applied technology, there is a growing need to protect quantum computers against information security attacks. This work identifies a new class of side-channel attacks against fault-tolerant quantum computers, in which the syndrome data that is sent to the decoder system is used to infer which computation (logical circuit) is taking place on the quantum computer. Our work introduces the concept of gate fingerprints, which describes those patterns present in syndrome data that indicate which logical operation took place on the quantum computer. We show different effects by which logical operations produce gate fingerprints by focusing on Clifford+T computation in the surface code. We then explore how gate fingerprint information can be used to make inferences about the circuits or algorithms run on a quantum computer. Our findings indicate that decoder systems can be a vector for side-channel attacks and thus to prevent this, decoder systems should either be secured or built by a trusted party.
Quantum computers promise computational advantages for many important problems across various application domains. Unfortunately, physical quantum devices are highly susceptible to errors that limit us from running most of these quantum applications. Quantum Error Correction (QEC) codes are required to implement Fault-Tolerant Quantum Computers (FTQC) on which computations can be performed without encountering errors. Error decoding is a critical component of quantum error correction and is responsible for transforming a set of qubit measurements generated by the QEC code, called the syndrome, into error locations and error types. For the feasibility of implementation, error decoders must not only identify errors with high accuracy, but also be fast and scalable to a large number of qubits. Unfortunately, most of the prior works on error decoding have focused primarily only on the accuracy and have relied on software implementations that are too slow to be of practical use. Furthermore, these studies only look at designing a single decoder and do not analyze the challenges involved in scaling the storage and bandwidth requirements when performing error correction in large systems with thousands of qubits.In this paper, we present AFS, an accurate, fast, and scalable decoder architecture that is designed to operate in the context of systems with hundreds of logical qubits. We present the hardware implementation of AFS, which is based on the Union Find decoding algorithm and employs a three-stage pipelined design. AFS provides orders of magnitude higher accuracy compared to recent SFQ-based hardware decoders (logical error rate of 6×10−10for physical error rate of 10−3) and low decoding latency (42ns on average), while being robust to measurement errors introduced while extracting syndromes during the QEC cycles. We also reduce the amount of decoding hardware required to perform QEC simultaneously on all the logical qubits by co-designing the micro-architecture across multiple decoding units. Our proposed Conjoined-Decoder Architecture (CDA) reduces the storage overhead by 70% (10MB to 2.8MB). Finally, we reduce the bandwidth overheads required to transmit syndromes from the qubits to the decoders by exploiting the sparsity in the syndromes and compressing the data. Our proposed Syndrome Compression reduces the bandwidth requirement by 30x, on an average.
Abstract This paper reports the first end-to-end fault-tolerant quantum computing stack to clear all four strict-FTQC requirements simultaneously on commodity superconducting NISQ silicon, rented through standard IBM Quantum cloud subscription with no purpose-built research machine, no custom decoder, and no magic-state distillation factory. The four requirements: (i) surface-code quantum error correction at distance d≥3 with logical-error rate below the unencoded baseline; (ii) a universal Clifford+T gate set executed via magic-state injection, with no arbitrary angle physical rotation carrying non-Clifford content on the wire (the algorithm-determined non-Clifford angle never fires on the silicon; the native RZ(θphys) on Heron fires only at Clifford-multiple angles required to compose H, S, T); (iii) heterogeneous primitive composition (teleportation, lattice-surgery CNOT, T-gate, logical memory) on a persistent encoded register; and (iv) runtime admissibility verification on every committed result. All five chips, five chemistry workloads spanning four molecules, and twenty-two governed runs in this paper were executed on the same primitive engine without architectural change. The architectural shift that makes this work on today’s hardware is the d=1 inversion: a 150-qubit governed encoded register held at substrate distance d=1 on the chip’s physical qubits, with logical fidelity preserved by Seed IQ execution governance over the encoded layer rather than by a larger code distance. Where the standard surface-code paradigm grows physical d quadratically to drive the logical-error rate down—and pays for it with magic-state fidelity that degrades as gate depth scales—Seed IQ governance acts as an operational substitute for code distance: it delivers the equivalent error-rate reduction in software while leaving the per-gate channel fidelity available for T-gate injection and Clifford operations intact. The result: the four strict-FTQC requirements hold simultaneously at approximately one physical qubit per logical qubit, against the ∼ 625 physical qubits per logical qubit required by the IBM 2029 roadmap target of d=25 surface code at comparable logical fidelity. Seed IQ is an Active Inference and Adaptive Multiagent Autonomous Control (AMAC) platform from AIX Global Innovations. Campaign summary. Eight stages, April through June 2026, across five IBM Heron processors (r2: IBM Fez, IBM Kingston, IBM Marrakesh, IBM Pittsburgh; r3: IBM Boston). April 9 — surface-code QEC: −88.5% LER reduction at d=3 on IBM Fez, −93.1% at d=5 where the MWPM+UF baseline collapsed, −60.9% at d=3 on 1.28°ø dirtier IBM Pittsburgh silicon. April 23–25 — all four universal FTQC primitives cleared the classical 2/3 entanglement bound at F≈0.99. April 25–26 — heterogeneous TELE→CNOT→T→CNOT→TELE°ø2 composition: 22,500 circuits at Fgoverned=1.0000, zero detected logical errors. May 7–9 — H2, 10 runs across 3 chips, 10/10 inside chem-acc, best ΔE=+0.0157mHa, two chips bit-identical to twelve decimals. May 23 —LiH, 3 runs across 3 chips, 3/3 inside chem-acc, two chips tied at ΔE=+0.056mHa. May 28–30 — H2O, 3 runs across 3 chips, 3/3 inside chem-acc at ΔE=+0.051mHa, all three bit-identical to twelve decimals. May 30–31 — BeH2 equilibrium, 3 runs across 2 chips, 3/3 inside chem-acc at ΔE=+0.000595mHa (2690.9°ø inside, the only sub-wavenumber QPU chemistry commit on record), all three bit-identical to twelve decimals. June 1 — BeH2 transition state (|cHF |2≈0.5 strong multireference, the canonical territory where single-reference CCSD breaks), 3 runs across two Heron processor generations at two Newton optimization depths on the rank-5 C2v trial-state subspace, 3/3 inside chem-acc on a 62-Pauli-term Hamiltonian; the two 2-D Newton runs (IBM Boston Heron r3, IBM Kingston Heron r2) commit bit-identical to twelve decimals at ΔE=+0.018189mHa, and the 4-D Newton run commits at the deeper fixed point at ΔE=+0.012643mHa (126.6°ø inside chem-acc, 1.6°ø inside the CCSD(T) gold band). Aggregate: twenty-two runs, 22/22 inside chemical accuracy. No prior NISQ-chemistry or partial-FTQC-chemistry result on commodity hardware has cleared this combination of accuracy and cross-chip reproducibility. Full per-stage detail in Åò4–Åò12.8. Compliance. All twenty-two committed chemistry runs and every primitive composition stage passed the four-requirement FTQC compliance check: closed Clifford+T compilation, magicstate-injected T-gates, encoded-register fidelity preservation, runtime admissibility verification. Fgoverned=1.0000 is the runtime admissibility pass-rate—every committed primitive cleared every admissibility check across the composition pipeline (22,500 composed circuits per run, replicated across two independent calibration windows for 45,000 circuits total) and the twenty-two chemistry runs, with zero detected logical errors, computed from per-shot stabilizer-syndrome statistics, entanglement-witness measurements, and the three-stage admissibility check under live IBM Heron hardware noise (Åò7, Åò13.13). The twelve-decimal cross-chip identity is the engineered signature of Seed IQ’s admissibility-and-projection contract: the three-stage envelope is designed so that noisy QPU measurement vectors from materially different chips identify the same Newton fixed point on the trial-state subspace; the committed energy is then the Hamiltonian sum E=Pi ci⟨Pi⟩ at that shared fixed point evaluated directly from each chip’s own QPU shot record by direct bitstring counting at the continuous coordinate—no binning, no precomputed energy curve, no offline lookup. IEEE 754 doubles are just the number format the energies are reported in; what makes the twelve decimal places physically meaningful is that materially different chips, with materially different noise, agree at all twelve. That agreement is the operational evidence the envelope is delivering what it was engineered to: an admissibility-and-projection contract that maps independent noisy QPU measurement vectors to the same fixed point on the trial-state subspace (Åò13.10, Åò14).
Quantum error correction (QEC) is indispensable for building scalable fault-tolerant quantum computers. Effective QEC demands stringent real-time decoding: the decoder must process syndrome measurements and determine corrections within a time scale--typically on the order of microseconds, to avoid data backlog. Scaling to large number of logical qubits further necessitates significant computational resources. In this work, we propose an architecture, called \emph{THQLink}, for real-time decoding of quantum error correction codes using high-performance computing (HPC) resources. The network connecting the HPC and the control system of quantum processing unit (QPU) is built on TH-Express and can be adapted to different quantum technologies and their associated control stacks. We report a round-trip latency of 2.944 μμμs on average, with an incremental overhead of 130 ns per additional hop. Using a parallel window strategy, we demonstrate real-time decoding (1 μμμs per QEC round) of the surface code up to distance 19 using a matching-based decoder on CPUs. Our work presents a scalable framework for real-time decoding in fault-tolerant quantum computing. It can be readily applied to quantum-centric supercomputers that feature tight integration between QPU and HPC resources, thereby enabling efficient support for hybrid quantum-classical algorithms and computation-intensive workloads offloaded from the QPU.
Practical applications of quantum computing depend on fault-tolerant devices that employ error correction. A promising quantum error-correcting code for large-scale quantum computing is the surface code. For this code, Fault-Tolerant Quantum Computing (FTQC) can be performed via lattice surgery, i.e. merging and splitting of encoded qubit patches on a 2D grid. Lattice surgery operations result in space-time patterns of activity that are defined in this work as access traces. This work demonstrates that the access traces reveal when, where, and how logical qubits interact. Leveraging this formulation, this work further introduces TraceQ, a tracebased reconstruction framework that is able to reconstruct the quantum circuit dataflow just by observing the patch activity at each trace entry. The framework is supported by heuristics for handling inherent ambiguity in the traces, and demonstrates its effectiveness on a range of synthetic fault-tolerant quantum benchmarks. The access traces can have applications in a wide range of scenarios, enabling analysis and profiling of execution of quantum programs and the hardware they run on. As one example use of TraceQ, this work investigates whether such traces can act as a side channel through which an observer can recover the circuit's structure and identify known subroutines in a larger program or even whole programs. The findings show that indeed the minimal access traces can be used to recover subroutines or even whole quantum programs with very high accuracy. Only a single trace per program execution is needed and the processing can be done fully offline. Along with the custom heuristics, advanced subgraph matching algorithms used in this work enable a high rate of locating the subroutines while executing in minimal time.
Quantum error correction (QEC) is transitioning from physical feasibility demonstrations to systems engineering challenges. Google has achieved below-threshold performance on distance-5/7 surface codes, while Riverlane and Rigetti have demonstrated hardware-integrated low-latency feedback loops. These milestones indicate that the core challenge of real-time decoding has shifted from algorithmic capability to system-level engineering. However, a substantial engineering gap remains between laboratory demonstrations and scalable fault-tolerant quantum computing (FTQC). This white paper addresses three questions: (1) Where are the real bottlenecks in real-time QEC: beyond average decoder speed, the constraints lie in QEC round time, tail latency, and end-to-end data path coordination; (2) How mature are mainstream decoder algorithms: we benchmark the major decoders for both surface codes and quantum low-density parity-check (qLDPC) codes, evaluating their real-time readiness; (3) What system stack do we propose: a six-layer reference architecture from syndrome acquisition to logical operations, with interface definitions and latency budget models. Our results quantify the gap between current decoder performance and real-time requirements, and identify the architectural choices needed to close it.