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Beyond the Dense Ceiling: VRAM-Resident Tiered Compression for Quantum Circuit Simulation on Consumer GPUs

Piero Jose Alarcon Dueñas

Published Jul 22, 2026• 0 citations
Publisher

Abstract

State-vector simulation of n qubits requires 2^n complex amplitudes, capping a 6 GB consumer GPU at 29 qubits. We present qubit, a quantum circuit simulator whose state vector is partitioned into blocks, each stored in one of three tiers (ZERO with no storage, COMPRESSED as block-scaled int16 at 4 B/amplitude, or FULL as complex64) and resident entirely in GPU memory: promotion and demotion are kernels, and the only host traffic is scheduling metadata and measurement scalars, in contrast to prior compression frameworks that stage compressed state in host memory. Quantization error is accumulated exactly on-device; because unitaries preserve norms, per-event errors compose linearly in L2 norm, giving a conservative a-priori fidelity bound F ≥ (1−D)²/(1+D)² for total injected error D. The bound is tight at low circuit depth and becomes loose as errors accumulate, so we pair it with a random-walk estimate and direct measurement, and use its inverse to turn a user-specified fidelity target into a compression budget the runtime never exceeds. Unlike structure-aware simulators (matrix product states, stabilizer methods, or Qrack), which shrink only low-entanglement states, this compresses the genuinely dense states that have no structure to exploit: on an RTX 3060 Laptop GPU (6 GB, dense complex64 ceiling 29 qubits) qubit holds a 29-qubit fully-dense state in half its footprint at measured fidelity 0.9998, and is 3.5–6× faster than Qrack on dense circuits on the same card, while the ZERO tier still captures sparse states exactly (a 31-qubit GHZ circuit in 1 MB). An automatic planner chooses among dense, entanglement-factorized, and tiered representations from a static analysis of the circuit, so the user declares qubits, gates, and a fidelity target, and nothing else. Code and data: https://github.com/ArubikU/qubit

DOI
10.5281/zenodo.21483389

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State-vector simulation of n qubits requires 2^n complex amplitudes, capping a 6 GB consumer GPU at 29 qubits. We present qubit, a quantum circuit simulator whose state vector is partitioned into blocks, each stored in one of three tiers (ZERO with no storage, COMPRESSED as block-scaled int16 at 4 B/amplitude, or FULL as complex64) and resident entirely in GPU memory: promotion and demotion are kernels, and the only host traffic is scheduling metadata and measurement scalars, in contrast to prior compression frameworks that stage compressed state in host memory. Quantization error is accumulated exactly on-device; because unitaries preserve norms, per-event errors compose linearly in L2 norm, giving a conservative a-priori fidelity bound F ≥ (1−D)²/(1+D)² for total injected error D. The bound is tight at low circuit depth and becomes loose as errors accumulate, so we pair it with a random-walk estimate and direct measurement, and use its inverse to turn a user-specified fidelity target into a compression budget the runtime never exceeds. Unlike structure-aware simulators (matrix product states, stabilizer methods, or Qrack), which shrink only low-entanglement states, this compresses the genuinely dense states that have no structure to exploit: on an RTX 3060 Laptop GPU (6 GB, dense complex64 ceiling 29 qubits) qubit holds a 29-qubit fully-dense state in half its footprint at measured fidelity 0.9998, and is 3.5–6× faster than Qrack on dense circuits on the same card, while the ZERO tier still captures sparse states exactly (a 31-qubit GHZ circuit in 1 MB). An automatic planner chooses among dense, entanglement-factorized, and tiered representations from a static analysis of the circuit, so the user declares qubits, gates, and a fidelity target, and nothing else. Code and data: https://github.com/ArubikU/qubit
Full-state quantum circuit simulation requires exponentially increased memory size to store the state vector as the number of qubits scales, presenting significant limitations in classical computing systems. Our paper introduces BMQSim, a novel state vector quantum simulation framework that employs lossy compression to address the memory constraints on graphics processing unit (GPU) machines. BMQSim effectively tackles four major challenges for state-vector simulation with compression: frequent compression/decompression, high memory movement overhead, lack of dedicated error control, and unpredictable memory space requirements. Our work proposes an innovative strategy of circuit partitioning to significantly reduce the frequency of compression occurrences. We introduce a pipeline that seamlessly integrates compression with data movement while concealing its overhead. Additionally, BMQSim incorporates the first GPU-based lossy compression technique with point-wise error control. Furthermore, BMQSim features a two-level memory management system, ensuring efficient and stable execution. Our evaluations demonstrate that BMQSim can simulate the same circuit with over 10 times less memory usage on average, achieving fidelity over 0.99 and maintaining comparable simulation time to other state-of-the-art simulators.
Quantum circuit simulations are applied in more and more circumstances as the quantum computing community becomes broader. It helps researchers to evaluate the quantum algorithms and relieve the burden of limited quantum computing resources. However, most of the state-of-the-art quantum simulators utilizes either CPU or GPU to store and calculate the state vector, which results in resources stravation. Morever, the mamximum number of qubits supported by simulator is bounded by the memory, since the memory utilization increases exponentially with the number of qubits. In this study, we leverage Heterogeneous computing to utilize both CPU and GPU to store and update state vectors. We also integrate lossy data compression to reduce memory requirements. Specifically, we develop a heterogeous framework that has a dynamic scheduler to fully utilize the computing resources. We apply lossy compression to chunked state vector to make the maximum number of qubits higher than the regular simulators, the compression also benifits the data movement between CPU and GPU.
Classical simulation of quantum circuits remains indispensable for algorithm development, hardware validation, and error analysis in the noisy intermediate-scale quantum (NISQ) era. However, state-vector simulation faces exponential memory scaling, with an n-qubit system requiring O(2^n) complex amplitudes, and existing simulators often lack the flexibility to exploit heterogeneous computing resources at runtime. This paper presents a GPU-accelerated quantum circuit simulation framework that introduces three contributions: (1) an empirical backend selection algorithm that benchmarks CuPy, PyTorch-CUDA, and NumPy-CPU backends at runtime and selects the optimal execution path based on measured throughput; (2) a directed acyclic graph (DAG) based gate fusion engine that reduces circuit depth through automated identification of fusible gate sequences, coupled with adaptive precision switching between complex64 and complex128 representations; and (3) a memory-aware fallback mechanism that monitors GPU memory consumption and gracefully degrades to CPU execution when resources are exhausted. The framework integrates with Qiskit, Cirq, PennyLane, and Amazon Braket through a unified adapter layer. Benchmarks on an NVIDIA A100-SXM4 (40 GiB) GPU demonstrate speedups of 64x to 146x over NumPy CPU execution for state-vector simulation of circuits with 20 to 28 qubits, with speedups exceeding 5x from 16 qubits onward. Hardware validation on an IBM quantum processing unit (QPU) confirms Bell state fidelity of 0.939, a five-qubit Greenberger-Horne-Zeilinger (GHZ) state fidelity of 0.853, and circuit depth reduction from 42 to 14 gates through the fusion pipeline. The system is designed for portability across NVIDIA consumer and data-center GPUs, requiring no vendor-specific compilation steps.
Abstract Statevector simulation of quantum circuits is fundamentally bounded by an expo-nential in the qubit count, which caps single-device simulation at around thirtyqubits regardless of how the arithmetic is laid out in hardware. The matrixproduct state (MPS) representation breaks that ceiling for circuits of boundedentanglement: its memory and time cost grow only linearly in the number ofqubits and polynomially in a single control parameter, the bond dimension χ.This paper presents a quantum circuit simulator built around an MPS engine thatruns its most expensive primitive, the two-site tensor contraction, on a XilinxAlveo U55C FPGA, with the numerically delicate singular value decomposition(SVD) executed by the host. We describe the engine end to end: an eight-bank,modulo-eight interleaved high-bandwidth-memory (HBM) tensor layout that fitswithin a strict nine-AXI-master routing budget; a double-precision HLS contrac-tion kernel that streams complex amplitudes directly from HBM; a co-designsplit that keeps every floating-point divide and square root off the FPGA crit-ical path, motivated by a concrete timing-closure failure we document; a hostbackend that performs SWAP routing, host-side SVD truncation, a bank-alignedallocator, and sequential conditional sampling in O(nχ2) per shot; and a four-card distributed mode that partitions the chain across devices with an O(χ2)boundary-tensor exchange. We then report what the system actually does. Forshallow, low-entanglement circuits the FPGA contraction is a negligible fractionof wall-clock time and classical measurement sampling on the host dominates;we show this directly rather than hiding it. As the bond dimension grows thepicture inverts, and at χ = 64 the FPGA contraction accounts for roughly sev-enty percent of the run, confirming that bond dimension, not qubit count, is theaxis on which this kind of accelerator earns its place. We push circuit width tofive hundred qubits, validate correctness against an independent Qiskit statevector oracle, and include a deliberate falsification experiment: zeroing the kernel output collapses the measured fidelity from above 0.99 to well below the threshold, demonstrating that the FPGA result is load-bearing and not decorative. Weclose with an honest account of the host-sampling bottleneck and the concretekernel and host changes it motivates.
Quantum circuit simulations enable researchers to develop quantum algorithms without the need for a physical quantum computer. Quantum computing simulators, however, all suffer from significant memory footprint requirements, which prevents large circuits from being simulated on classical super-computers. In this paper, we explore different lossy compression strategies to substantially shrink quantum circuit tensors in the QTensor package (a state-of-the-art tensor network quantum circuit simulator) while ensuring the reconstructed data satisfy the user-needed fidelity.Our contribution is fourfold. (1) We propose a series of optimized pre- and post-processing steps to boost the compression ratio of tensors with a very limited performance overhead. (2) We characterize the impact of lossy decompressed data on quantum circuit simulation results, and leverage the analysis to ensure the fidelity of reconstructed data. (3) We propose a configurable compression framework for GPU based on cuSZ and cuSZx, two state-of-the-art GPU-accelerated lossy compressors, to address different use-cases: either prioritizing compression ratios or prioritizing compression speed. (4) We perform a comprehensive evaluation by running 9 state-of-the-art compressors on an NVIDIA A100 GPU based on QTensor-generated tensors of varying sizes. When prioritizing compression ratio, our results show that our strategies can increase the compression ratio nearly 10 times compared to using only cuSZ. When prioritizing throughput, we can perform compression at the comparable speed as cuSZx while achieving 3-4× higher compression ratios. Decompressed tensors can be used in QTensor circuit simulation to yield a final energy result within 1-5% of the true energy value.
Monte-Carlo trajectory (quantum-jump) methods are the practical route to simulating noisy quantum circuits once the exact density-matrix method is precluded by its 4n4^n4n memory cost. Their bottleneck is estimator variance: resolving one expectation value can demand thousands of trajectories. Recent tensor-network work shows that \emph{variance-reduced unravelings} -- projector and analog sampling -- sharply cut this variance, but only on CPU matrix-product-state backends, with no path into production tooling. We implement both unravelings on a \emph{GPU dense-statevector} trajectory engine and validate them against the exact density matrix (ideal-circuit fidelity 1−2.2×10−161-2.2\times10^{-16}1−2.2×10−16; 1/N1/\sqrt{N}1/N​ convergence; all unravelings unbiased to trace distance <0.01<0.01<0.01). On a single consumer GPU, projector unraveling reaches a target standard error with 20.8×20.8\times20.8× fewer trajectories than Qiskit-Aer's \texttt{batched\_shots\_gpu} at n=10n=10n=10, a factor that holds at 191919--26×26\times26× across n=8n=8n=8--202020. A regime map places analog sampling optimal at weak noise and projector at strong noise, crossing near γt≈0.35γt\approx0.35γt≈0.35. We further report a systems finding: Qiskit-Aer applies noise at the \emph{channel} level and reconstructs a canonical Kraus decomposition at apply time, discarding any user-supplied unraveling, so variance-reduced unravelings cannot be delivered through its public API. Because Aer's Born-rule collapse machinery already exists, we specify a minimal change that would unlock the technique in production.