Abstract Energy-efficient rapid single flux quantum (ERSFQ) circuits suppress the dominant static power dissipation of Rapid SFQ logic by replacing bias resistors with current-limiting bias Josephson junctions (JJs) and inductors. In practice, however, these JJs introduce power dissipation in the DC bias network due to switching events required to correct data-dependent phase imbalances, with dissipation often comparable to that of dynamic power. This paper presents xeSFQ, a new SFQ logic family that integrates alternating SFQ (xSFQ) encoding with ERSFQ biasing. By enforcing a single pulse per line per logical cycle, xeSFQ maintains uniform phase across the circuit, thereby eliminating bias JJ switching during operation and achieving zero bias network power dissipation. Extensive analog simulations and logic synthesis results, from individual gates to ISCAS and EPFL benchmarks, validate this hypothesis and demonstrate the efficiency and scalability advantages of the proposed approach.
Abstract Energy-efficient rapid single flux quantum (ERSFQ) circuits suppress the dominant static power dissipation of Rapid SFQ logic by replacing bias resistors with current-limiting bias Josephson junctions (JJs) and inductors. In practice, however, these JJs introduce power dissipation in the DC bias network due to switching events required to correct data-dependent phase imbalances, with dissipation often comparable to that of dynamic power. This paper presents xeSFQ, a new SFQ logic family that integrates alternating SFQ (xSFQ) encoding with ERSFQ biasing. By enforcing a single pulse per line per logical cycle, xeSFQ maintains uniform phase across the circuit, thereby eliminating bias JJ switching during operation and achieving zero bias network power dissipation. Extensive analog simulations and logic synthesis results, from individual gates to ISCAS and EPFL benchmarks, validate this hypothesis and demonstrate the efficiency and scalability advantages of the proposed approach.
Energy-efficient rapid single flux quantum (ERSFQ) circuits have become a viable alternative for the implementation of superconducting circuits due to a large amount of static power consumption in RSFQ circuits. ERSFQ circuits are built upon the popular RSFQ logic circuits by replacing the power-dissipating resistor bias network with a bias network consisting of active devices. In this paper, a simulation study of ERSFQ biasing scheme is carried out by building simulation test benches for both synchronous and asynchronous ERSFQ circuits. A study is carried out to present the optimum value of biasing inductance, influence of the feeding Josephson transmission line (FJTL) and the effect of its size, the effect of the feeding clock frequency, and the effect of the circuit operating frequency. An innovative clock-choking mechanism using magnetic Josephson junctions is also proposed for the FJTL in the case of no logic circuit activity for a current-recycling circuit block, which would help in eliminating the dynamic power consumed due to the switching of bias junctions in a logic circuit. Simulation results for current recycling ERSFQ circuits are presented along with a strategy for implementing large superconducting circuits.
Superconducting single flux quantum (SFQ) circuits have been shown to offer huge advantages that are ideal for high performance computing applications. These circuits can operate at very high frequencies (tens of GHz) but consume very low power (from nanowatts to microwatts per gate). Energy-efficient SFQ (ERSFQ) circuits, evolved from traditional rapid SFQ (RSFQ) circuits, were invented with the goal of elimination of static power dissipation. When compared with RSFQ circuits, ERSFQ circuits require a new biasing network that includes biasing Josephson junction(s), biasing inductor(s), and feeding Josephson transmission line(s). Some general suggestions on how to design the network have been offered, but a detailed analysis and optimization scenario for the network is still to be provided. In this paper, we first optimize the previously reported DC-biased two-Josephson junction per bit RSFQ shift register circuit, which can be used to provide a more robust, energy-efficient, and high memory capacity storage unit. The simulated power dissipation of 16-bit RSFQ shift register is 0.45 μW per bit when operating at 21.7 GHz. We then convert the RSFQ-based shift register into an ERSFQ structure and investigate the effects of the ERSFQ bias network on the margins of the ERSFQ circuit. Finally, we propose a more comprehensive optimization method for the ERSFQ biasing network.
High current requirements in single flux quantum (SFQ) circuits pose scalability challenges, contributing to issues such as high thermal loads, static power dissipation, and increased sensitivity to flux trapping under non-ideal shielding or cool down conditions. AC biasing, successfully used in other superconductive logic families, has been integrated into rapid single flux quantum (RSFQ) circuits and typically includes AC-to-DC converters, introducing area and complexity overhead. This work proposes an alternative method for applying AC biasing to existing RSFQ circuits using inductively coupled bias junctions, eliminating the need for AC-to-DC converters. This approach also combines resistive DC biasing with inductive AC biasing, reducing static power dissipation. The proposed approach targets clock splitters, which are significant contributors to on-chip current demand, achieving an average 94% reduction in splitter current and a 62% reduction in overall system current with a Josephson junction overhead of 6.5%. The technique is compatible with conventional RSFQ system architectures and logic families while significantly enhancing energy efficiency and scalability.
Biasing remains one of the key scalability bottle necks in superconducting digital circuits, as traditional DC bias networks impose excessive power dissipation, large direct current requirements resulting in significant power overhead. Fast Phase Logic (FPL), an all-Josephson Junction (JJ) logic family, achieves ultra-high density by eliminating resistors and large inductors; however, existing FPL designs still rely on DC bias. This paper introduces a novel architecture: AC-biased FPL (ACFPL), which integrates single-phase AC/SFQ converters with FPL cells to deliver bias currents as quantized pulses, thereby eliminating the need for a global DC distribution network. Circuit-level simulations at 10 GHz demonstrate that AC biasing achieves up to 25× lower power consumption compared to DC bias for RSFQ circuits, and 14.3× reduction in power consumption for FPL circuits in our design-under-test (DUT), which combines FPL JTL, FPL DFF, and FPL AND cells. These results estab lish ACFPL as a scalable and energy-efficient alternative for large-scale superconducting digital systems, effectively combining compact FPL cell design with practical AC/SFQ bias delivery, allowing superconductor VLSI.
To improve circuit density and minimize static power dissipation in Single Flux Quantum (SFQ) circuits, this work investigates the application of inductively biased, unshunted Josephson transmission lines (JTLs) which achieve zero static power, compared with regular resistively biased JTLs. Both simulation and experiment results confirm that unshunted JTLs can reliably propagate SFQ pulses with a bias current margin larger than 50%. Based on this, a new fabrication process has been developed featuring eight niobium (Nb) layers, including two Nb/Al-AlOx/Nb junction layers, a dedicated bias-inductor layer, and dual DC-power layers. The vertical functional separation allows 2 active layers. The 1stactive layer uses conventional shunted JJs for logic gates, while the 2nduses unshunted JTLs with inductive bias. This configuration eliminates static power in the interconnect network and simplifies thermal management in stacked Rapid SFQ (RSFQ) architectures. A ten-stage unshunted JTL chain and a hybrid half-adder were designed and demonstrated. Measurements show a 66.7% reduction in static power and a 64.7% reduction in area compared with the Chinese Academy of Scienceconventional single-JJ-layer process. These results verify, for the first time, that inductively biased unshunted interconnects can be monolithically integrated with standard RSFQ logic, offering a scalable path toward ultra-dense, lower-power multilayer superconducting circuits.
Energy efficiency has become the primary parameter for the design of next-generation single flux quantum (SFQ) circuits. This, however, needs to be balanced with optimization for clock speed and bias margins. Here, we experimentally study the tradeoff between circuit activity, energy efficiency, and bias margins for zero static power dissipation ERSFQ circuits. For ERSFQ, dc power is provided by a Josephson transmission line (JTL) called a “feeding” JTL (FJTL), which acts as a voltage source. As a test case, shift registers and multiplexers were laid out and fabricated in both HYPRES's and MIT-LL's 10-kA/cm2fabrication processes and tested at low (~kHz) and high (~GHz) clock frequencies. The functional bias margins for these circuits increase significantly from +/-4% to over +/-19% when the Josephson junction count in the FJTL was increased to ~30% of total dc bias current of the circuit. Based on our findings, we discuss how to optimize ERSFQ circuits for both energy efficiency and dc bias margins.