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Applied Physics Letters

A tunable coincidence counter based on superconducting nanowire cryotrons

Nai‐Tao Liu, Qingyuan Zhao, Y Huang, Long Wang, Zhen Liu, Jie Deng, Fan Yang, Sai‐Ying Ru, LI Zhen-guo, Yao-Yao Pan, Yu Nie, S Q Wang, Kang-He Lv, Xuecou Tu, Xiaoqing Jia, Labao Zhang, Jian Chen, Lin Kang, Peiheng Wu

Published Jun 29, 2026• 0 citations
Publisher

Abstract

Single-photon coincidence counters are essential components in integrated quantum photonics, enabling efficient logic discrimination and real-time error correction at the chip level. However, monolithic integration at cryogenic temperature remains challenging. Here, we demonstrate a coincidence counter based on superconducting nanowire cryotrons (nTron). The circuit comprises five nTron devices, including delay gates, buffer gates, and an AND gate, achieving a maximum bias margin of 22% at a bit error rate (BER) of 10−5. Operating at 1 MHz, the counter exhibits a static power consumption of 282 nW and a dynamic power consumption of approximately 2 nW at a maximum operation frequency of 17 MHz. The coincidence time window is tunable, with a minimum width below 1 ns, and its position can be adjusted via bias currents. This design offers compatibility with superconducting nanowire single-photon detectors in fabrication and operation, supporting monolithic integration for scalable quantum photonic systems.

DOI
10.1063/5.0334034

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Single-photon coincidence counters are essential components in integrated quantum photonics, enabling efficient logic discrimination and real-time error correction at the chip level. However, monolithic integration at cryogenic temperature remains challenging. Here, we demonstrate a coincidence counter based on superconducting nanowire cryotrons (nTron). The circuit comprises five nTron devices, including delay gates, buffer gates, and an AND gate, achieving a maximum bias margin of 22% at a bit error rate (BER) of 10−5. Operating at 1 MHz, the counter exhibits a static power consumption of 282 nW and a dynamic power consumption of approximately 2 nW at a maximum operation frequency of 17 MHz. The coincidence time window is tunable, with a minimum width below 1 ns, and its position can be adjusted via bias currents. This design offers compatibility with superconducting nanowire single-photon detectors in fabrication and operation, supporting monolithic integration for scalable quantum photonic systems.
Scalable superconducting nanowire single photon detector (SNSPDs) arrays require cryogenic digital circuits for multiplexing the output detection pulses. Among existing superconducting digital devices, superconducting nanowire cryotron (nTron) is a three-terminal device with an ultra-compact size, which is promising for large scale monolithic integration. In this report, in order to evaluate the potential and possibility of using nTrons for reading and digitizing SNSPD signals, we characterized the grey zone, speed, timing jitter and power dissipation of a proper designed nTron. With a DC bias on the gate, the nTron can be triggered by a few μA high and nanoseconds wide input signal, showing the nTron was capable of reading an SNSPD pulse at the same signal level. The timing jitter depended on the input signal level. For a 20 μA high and 5 ns wide input pulse, the timing jitter was 33.3 ps, while a typical SNSPD's jitter was around 50 ps. With removing the serial inductors and operating it in an AC bias mode. The nTron was demonstrated to be operated at a clock frequency of 615.4 MHz, which was faster than the maximum counting rate of a typical SNSPD. In additional, with a 50 Ω bias resistor and biased at 17.6 μA, the nTron had a total power dissipation of 19.7 nW. Although RSFQ circuits are faster than nTrons, for reading SNSPD or other detector arrays that demands less operation speed, our results suggest a digital circuit made from nTrons could be another promising alternative.
Scaling photonic quantum-information platforms requires arrays of superconducting nanowire single-photon detectors (SNSPDs) for feedforward control, in which optical operations are conditioned on Bell-state measurements relying on photon-coincidence detections. On-chip superconducting cryotron electronics, performing logic on detector outputs and driving optical modulators, could reduce latency and room-temperature interconnect complexity for feedforward schemes. To date, no cryotron circuits designed for this purpose have been demonstrated. We demonstrate a bias-programmable logic gate based on three nanocryotrons (nTrons) that implements selectable AND (coincidence), XOR (odd-parity), and OR functions. It operates on two electrical pulses at 4.2 K, with bit-error rates below 10−310^{-3}10−3, bias margins up to ±21.7%\pm21.7\%±21.7%, and operation extending to 25 MHz over narrower bias windows. It performs coincidence and odd-parity detection on two SNSPDs' outputs with bit-error rates below 3.2×10−23.2 \times 10^{-2}3.2×10−2. As proof-of-concept, we show that nTrons can drive capacitive loads up to 1.15 V, potentially enabling compatibility with electro-optic modulators in feedforward schemes.
Superconducting digital circuits are promising technologies that can overcome bottlenecks in both classical and quantum computation due to their ultra-high operation speed and extremely low power dissipation. Superconducting nanowire cryotrons (nTrons) are emerging as one type of superconductor switching devices, offering advantages complementary to conventional Josephson junctions. Achieving monolithic integration of a reasonable number of nTrons into a functional digital circuit is a crucial step to extend its application. In this study, we constructed a monolithic integrated nTron-based binary encoder, which includes input fanout circuits, on-chip biasing, combinational logic routing and multi-gate nTrons. This represents a monolithic nTron digital circuit comprising 137 nTron gates, 424 resistors, 274 inductors, and 164 vias developed using a two-superconducting-layer fabrication process. The performance of this monolithic nTron encoder surpasses that of our previously demonstrated circuit with discrete nTron components. The maximum bias margin is 28% for the fanout circuit and 60% for the multi-gate nTron when using a signal generator, while the minimum timing jitter is 40 ps. The total power dissipation mainly from biasing resistors is 19.6 μW, making it more power efficient than RSFQ encoders. The encoder is then packaged and connected with a superconducting nanowire single-photon detector array for demonstrating its function of addressing pixel locations. Compared to the conventional readout, the nTron encoder shows a minimum readout error rate lower than 10−4 and reduces the readout RF lines from 15 to 4. The design and fabrication technologies could enrich integrated nTron digital circuits beyond current limits and promote their applications in classical and quantum systems.
Abstract Many classic and quantum devices need to operate at cryogenic temperatures, demanding advanced cryogenic digital electronics for processing the input and output signals on a chip to extend their scalability and performance. Here, we report a superconducting binary encoder with ultralow power dissipation and ultracompact size. We introduce a multigate superconducting nanowire cryotron (nTron) that functions as an 8-input OR gate within a footprint of approximately 0.5 μm2. Four cryotrons compose a 4-bit encoder that has a bias margin of 18.9%, an operation speed greater than 250 MHz, an average switching jitter of 75 ps, and a power dissipation of less than 1 μW. We apply this encoder to read out a superconducting-nanowire single-photon detector array whose pixel location is digitized into a 4-bit binary address. The small size of the nanowire combined with the low power dissipation makes nTrons promising for future monolithic integration.
The superconducting nanowire single-photon detector (SNSPD) is a leading technology for quantum information science applications using photons, and is finding increasing uses in photon-starved classical imaging applications. Critical detector characteristics, such as timing resolution (jitter), reset time, and maximum count rate, are heavily influenced by the readout electronics that sense and amplify the photon detection signal. We describe a readout circuit for SNSPDs using commercial off-the-shelf amplifiers operating at cryogenic temperatures. Our design demonstrates a 35 ps timing resolution and a maximum count rate of over 2 × 107 counts per second, while maintaining <3 mW power consumption per channel, making it suitable for a multichannel readout.
Superconducting nanowire single-photon detectors (SNSPDs) show near unity efficiency, low dark count rate, and short recovery time. Combining these characteristics with temporal control of SNSPDs broadens their applications as in active de-latching for higher dynamic range counting or temporal filtering for pump-probe spectroscopy or LiDAR. To that end, we demonstrate active gating of an SNSPD with a minimum off-to-on rise time of 2.4 ns and a total gate length of 5.0 ns. We show how the rise time depends on the inductance of the detector in combination with the control electronics. The gate window is demonstrated to be fully and freely, electrically tunable up to 500 ns at a repetition rate of 1.0 MHz, as well as ungated, free-running operation. Control electronics to generate the gating are mounted on the 2.3 K stage of a closed-cycle sorption cryostat, while the detector is operated on the cold stage at 0.8 K. We show that the efficiency and timing jitter of the detector is not altered during the on-time of the gating window. We exploit gated operation to demonstrate a method to increase in the photon counting dynamic range by a factor 11.2, as well as temporal filtering of a strong pump in an emulated pump-probe experiment.