Abstract Many classic and quantum devices need to operate at cryogenic temperatures, demanding advanced cryogenic digital electronics for processing the input and output signals on a chip to extend their scalability and performance. Here, we report a superconducting binary encoder with ultralow power dissipation and ultracompact size. We introduce a multigate superconducting nanowire cryotron (nTron) that functions as an 8-input OR gate within a footprint of approximately 0.5 μm2. Four cryotrons compose a 4-bit encoder that has a bias margin of 18.9%, an operation speed greater than 250 MHz, an average switching jitter of 75 ps, and a power dissipation of less than 1 μW. We apply this encoder to read out a superconducting-nanowire single-photon detector array whose pixel location is digitized into a 4-bit binary address. The small size of the nanowire combined with the low power dissipation makes nTrons promising for future monolithic integration.
Abstract Many classic and quantum devices need to operate at cryogenic temperatures, demanding advanced cryogenic digital electronics for processing the input and output signals on a chip to extend their scalability and performance. Here, we report a superconducting binary encoder with ultralow power dissipation and ultracompact size. We introduce a multigate superconducting nanowire cryotron (nTron) that functions as an 8-input OR gate within a footprint of approximately 0.5 μm2. Four cryotrons compose a 4-bit encoder that has a bias margin of 18.9%, an operation speed greater than 250 MHz, an average switching jitter of 75 ps, and a power dissipation of less than 1 μW. We apply this encoder to read out a superconducting-nanowire single-photon detector array whose pixel location is digitized into a 4-bit binary address. The small size of the nanowire combined with the low power dissipation makes nTrons promising for future monolithic integration.
Superconducting digital circuits are promising technologies that can overcome bottlenecks in both classical and quantum computation due to their ultra-high operation speed and extremely low power dissipation. Superconducting nanowire cryotrons (nTrons) are emerging as one type of superconductor switching devices, offering advantages complementary to conventional Josephson junctions. Achieving monolithic integration of a reasonable number of nTrons into a functional digital circuit is a crucial step to extend its application. In this study, we constructed a monolithic integrated nTron-based binary encoder, which includes input fanout circuits, on-chip biasing, combinational logic routing and multi-gate nTrons. This represents a monolithic nTron digital circuit comprising 137 nTron gates, 424 resistors, 274 inductors, and 164 vias developed using a two-superconducting-layer fabrication process. The performance of this monolithic nTron encoder surpasses that of our previously demonstrated circuit with discrete nTron components. The maximum bias margin is 28% for the fanout circuit and 60% for the multi-gate nTron when using a signal generator, while the minimum timing jitter is 40 ps. The total power dissipation mainly from biasing resistors is 19.6 μW, making it more power efficient than RSFQ encoders. The encoder is then packaged and connected with a superconducting nanowire single-photon detector array for demonstrating its function of addressing pixel locations. Compared to the conventional readout, the nTron encoder shows a minimum readout error rate lower than 10−4 and reduces the readout RF lines from 15 to 4. The design and fabrication technologies could enrich integrated nTron digital circuits beyond current limits and promote their applications in classical and quantum systems.
Scalable superconducting nanowire single photon detector (SNSPDs) arrays require cryogenic digital circuits for multiplexing the output detection pulses. Among existing superconducting digital devices, superconducting nanowire cryotron (nTron) is a three-terminal device with an ultra-compact size, which is promising for large scale monolithic integration. In this report, in order to evaluate the potential and possibility of using nTrons for reading and digitizing SNSPD signals, we characterized the grey zone, speed, timing jitter and power dissipation of a proper designed nTron. With a DC bias on the gate, the nTron can be triggered by a few μA high and nanoseconds wide input signal, showing the nTron was capable of reading an SNSPD pulse at the same signal level. The timing jitter depended on the input signal level. For a 20 μA high and 5 ns wide input pulse, the timing jitter was 33.3 ps, while a typical SNSPD's jitter was around 50 ps. With removing the serial inductors and operating it in an AC bias mode. The nTron was demonstrated to be operated at a clock frequency of 615.4 MHz, which was faster than the maximum counting rate of a typical SNSPD. In additional, with a 50 Ω bias resistor and biased at 17.6 μA, the nTron had a total power dissipation of 19.7 nW. Although RSFQ circuits are faster than nTrons, for reading SNSPD or other detector arrays that demands less operation speed, our results suggest a digital circuit made from nTrons could be another promising alternative.
Single-photon coincidence counters are essential components in integrated quantum photonics, enabling efficient logic discrimination and real-time error correction at the chip level. However, monolithic integration at cryogenic temperature remains challenging. Here, we demonstrate a coincidence counter based on superconducting nanowire cryotrons (nTron). The circuit comprises five nTron devices, including delay gates, buffer gates, and an AND gate, achieving a maximum bias margin of 22% at a bit error rate (BER) of 10−5. Operating at 1 MHz, the counter exhibits a static power consumption of 282 nW and a dynamic power consumption of approximately 2 nW at a maximum operation frequency of 17 MHz. The coincidence time window is tunable, with a minimum width below 1 ns, and its position can be adjusted via bias currents. This design offers compatibility with superconducting nanowire single-photon detectors in fabrication and operation, supporting monolithic integration for scalable quantum photonic systems.
Abstract A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10 −19 J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μ m × 7 μ m in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.
We designed, fabricated, and tested a one-dimensional array of superconducting-nanowire single-photon detectors, integrated with on-chip inductors and resistors. The architecture is suitable for monolithic integration on a single chip operated in a cryogenic environment, and inherits the characteristics of individual superconducting-nanowire single-photon detectors. We demonstrated a working array with four pixels showing position discrimination and a timing jitter of 124 ps. The electronic crosstalk between the pixels in the array was negligible.
A fan-out circuit is a basic block for scaling up digital circuits for overcoming the limited driving capability of a single logic gate. It is particularly important for superconducting digital circuits as the driving power is typically weak for having high energy efficiency. Here, we design and fabricate a fan-out circuit for a superconducting nanowire cryotron (nTron) digital circuit. A classic splitter tree architecture is adopted. To transmit switching signal and avoid crosstalk among nTrons, we introduced an “R–L–R” interface circuit. Experimentally, a two-stage splitter tree of a fan-out number of four was demonstrated. Correct operation was observed with a minimum bit error rate (BER) of 10−6. The bias margin was 10% at BER of 10−4. The average time jitter was 82 ps. Moreover, crosstalk was not observed. Based on these results, we envision that the fan-out circuit can be used in future development of superconducting-nanowire-based circuits.