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Scientific Reports

Characterize the switching performance of a superconducting nanowire cryotron for reading superconducting nanowire single photon detectors

Kai Zheng, Qingyuan Zhao, Ling-Dong Kong, Shi Chen, Hai-Yang-Bo Lu, Xuecou Tu, Labao Zhang, Xiaoqing Jia, Jian Chen, Lin Kang, Peiheng Wu

Published Nov 8, 2019• 17 citations
Publisher

Abstract

Scalable superconducting nanowire single photon detector (SNSPDs) arrays require cryogenic digital circuits for multiplexing the output detection pulses. Among existing superconducting digital devices, superconducting nanowire cryotron (nTron) is a three-terminal device with an ultra-compact size, which is promising for large scale monolithic integration. In this report, in order to evaluate the potential and possibility of using nTrons for reading and digitizing SNSPD signals, we characterized the grey zone, speed, timing jitter and power dissipation of a proper designed nTron. With a DC bias on the gate, the nTron can be triggered by a few μA high and nanoseconds wide input signal, showing the nTron was capable of reading an SNSPD pulse at the same signal level. The timing jitter depended on the input signal level. For a 20 μA high and 5 ns wide input pulse, the timing jitter was 33.3 ps, while a typical SNSPD's jitter was around 50 ps. With removing the serial inductors and operating it in an AC bias mode. The nTron was demonstrated to be operated at a clock frequency of 615.4 MHz, which was faster than the maximum counting rate of a typical SNSPD. In additional, with a 50 Ω bias resistor and biased at 17.6 μA, the nTron had a total power dissipation of 19.7 nW. Although RSFQ circuits are faster than nTrons, for reading SNSPD or other detector arrays that demands less operation speed, our results suggest a digital circuit made from nTrons could be another promising alternative.

DOI
10.1038/s41598-019-52874-3

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Scalable superconducting nanowire single photon detector (SNSPDs) arrays require cryogenic digital circuits for multiplexing the output detection pulses. Among existing superconducting digital devices, superconducting nanowire cryotron (nTron) is a three-terminal device with an ultra-compact size, which is promising for large scale monolithic integration. In this report, in order to evaluate the potential and possibility of using nTrons for reading and digitizing SNSPD signals, we characterized the grey zone, speed, timing jitter and power dissipation of a proper designed nTron. With a DC bias on the gate, the nTron can be triggered by a few μA high and nanoseconds wide input signal, showing the nTron was capable of reading an SNSPD pulse at the same signal level. The timing jitter depended on the input signal level. For a 20 μA high and 5 ns wide input pulse, the timing jitter was 33.3 ps, while a typical SNSPD's jitter was around 50 ps. With removing the serial inductors and operating it in an AC bias mode. The nTron was demonstrated to be operated at a clock frequency of 615.4 MHz, which was faster than the maximum counting rate of a typical SNSPD. In additional, with a 50 Ω bias resistor and biased at 17.6 μA, the nTron had a total power dissipation of 19.7 nW. Although RSFQ circuits are faster than nTrons, for reading SNSPD or other detector arrays that demands less operation speed, our results suggest a digital circuit made from nTrons could be another promising alternative.
Superconducting digital circuits are promising technologies that can overcome bottlenecks in both classical and quantum computation due to their ultra-high operation speed and extremely low power dissipation. Superconducting nanowire cryotrons (nTrons) are emerging as one type of superconductor switching devices, offering advantages complementary to conventional Josephson junctions. Achieving monolithic integration of a reasonable number of nTrons into a functional digital circuit is a crucial step to extend its application. In this study, we constructed a monolithic integrated nTron-based binary encoder, which includes input fanout circuits, on-chip biasing, combinational logic routing and multi-gate nTrons. This represents a monolithic nTron digital circuit comprising 137 nTron gates, 424 resistors, 274 inductors, and 164 vias developed using a two-superconducting-layer fabrication process. The performance of this monolithic nTron encoder surpasses that of our previously demonstrated circuit with discrete nTron components. The maximum bias margin is 28% for the fanout circuit and 60% for the multi-gate nTron when using a signal generator, while the minimum timing jitter is 40 ps. The total power dissipation mainly from biasing resistors is 19.6 μW, making it more power efficient than RSFQ encoders. The encoder is then packaged and connected with a superconducting nanowire single-photon detector array for demonstrating its function of addressing pixel locations. Compared to the conventional readout, the nTron encoder shows a minimum readout error rate lower than 10−4 and reduces the readout RF lines from 15 to 4. The design and fabrication technologies could enrich integrated nTron digital circuits beyond current limits and promote their applications in classical and quantum systems.
Detecting spatial and temporal information of individual photons is a crucial technology in today's quantum information science. Among the existing single-photon detectors, superconducting nanowire single-photon detectors (SNSPDs) have been demonstrated with a sub-50 ps timing jitter, near unity detection efficiency1, wide response spectrum from visible to infrared and ~10 ns reset time. However, to gain spatial sensitivity, multiple SNSPDs have to be integrated into an array, whose spatial and temporal resolutions are limited by the multiplexing circuit. Here, we add spatial sensitivity to a single nanowire while preserving the temporal resolution from an SNSPD, thereby turning an SNSPD into a superconducting nanowire single-photon imager (SNSPI). To achieve an SNSPI, we modify a nanowire's electrical behavior from a lumped inductor to a transmission line, where the signal velocity is slowed down to 0.02c (where c is the speed of light). Consequently, we are able to simultaneously read out the landing locations and arrival times of the photons from the output electrical pulses using only two connections. We have demonstrated single-photon imaging by using a 19.7 mm long SNSPI, which is meandered into an imaging area of 286 {\mu}m*193 {\mu}m. The nanowire has a temporal resolution of 50 ps for detecting 1.5 {\mu}m photons. The 2D spatial resolution is 13.0 {\mu}m in the vertical direction and 5.6 {\mu}m in the horizontal direction. The maximum number of resolvable locations (i.e., the effective number of pixels) in such a long nanowire is calculated to be 590. Rather than operating an individual detector in a scanning mode or using SPD arrays, this SNSPI gives an alternative approach to taking large-scale single-photon images and measuring temporal and spatial correlation.
Abstract Many classic and quantum devices need to operate at cryogenic temperatures, demanding advanced cryogenic digital electronics for processing the input and output signals on a chip to extend their scalability and performance. Here, we report a superconducting binary encoder with ultralow power dissipation and ultracompact size. We introduce a multigate superconducting nanowire cryotron (nTron) that functions as an 8-input OR gate within a footprint of approximately 0.5 μm2. Four cryotrons compose a 4-bit encoder that has a bias margin of 18.9%, an operation speed greater than 250 MHz, an average switching jitter of 75 ps, and a power dissipation of less than 1 μW. We apply this encoder to read out a superconducting-nanowire single-photon detector array whose pixel location is digitized into a 4-bit binary address. The small size of the nanowire combined with the low power dissipation makes nTrons promising for future monolithic integration.
Single-photon coincidence counters are essential components in integrated quantum photonics, enabling efficient logic discrimination and real-time error correction at the chip level. However, monolithic integration at cryogenic temperature remains challenging. Here, we demonstrate a coincidence counter based on superconducting nanowire cryotrons (nTron). The circuit comprises five nTron devices, including delay gates, buffer gates, and an AND gate, achieving a maximum bias margin of 22% at a bit error rate (BER) of 10−5. Operating at 1 MHz, the counter exhibits a static power consumption of 282 nW and a dynamic power consumption of approximately 2 nW at a maximum operation frequency of 17 MHz. The coincidence time window is tunable, with a minimum width below 1 ns, and its position can be adjusted via bias currents. This design offers compatibility with superconducting nanowire single-photon detectors in fabrication and operation, supporting monolithic integration for scalable quantum photonic systems.
Superconducting series nanowire single-photon detectors (SNDs) have been used for resolving photon numbers. But it can also exhibit a higher counting rate than a single superconducting nanowire single-photon detector (SNSPD), because the serial architecture allows multiple detectors working in parallel and the inductance of each pixel is reduced. In this paper, we found each pixel of the SND could reset fast although the whole detector took a much longer time for recovering. Therefore, the speed of an SND with a large kinetic inductance of 1.25 μH was characterized and compared to a standard SNSPD with the same total inductance. By measuring the detected photon rate over the input photon rate, we obtained a photon counting rate enhancement by 7.5 times. Meanwhile, the timing jitter of the SND was 63 ps at single photon detection regime. Our results show that the series structure and the readout scheme are quite practical in realizing high speed single-photon detectors besides resolving photon numbers.
This paper presents a scalable cryogenic readout solution for Superconducting Nanowire Single-Photon Detectors (SNSPDs) tailored for the readout of color-center-based qubits. The readout circuit, wire-bonded directly to the SNSPD, utilizes high input impedance to boost the signal amplitude, hence reducing the power consumption, and active quenching to prevent the latching induced by the high impedance. Fabricated in 40-nm CMOS in a0.14−mm20.14-\text{mm}^{2}0.14−mm2active area, the proposed system demonstrates competitive performance at 0.1 K, featuring low jitter [<60ps<60 \text{ps}<60psFull Width at Half Maximum (FWHM)], high speed (dead time≈5ns\approx 5 \text{ns}≈5ns) and low dark count rate (<1Hz<1 \text{Hz}<1Hz), while dissipating only20μW20 \mu \mathrm{W}20μW. Such an ultra-low power and compact area enables the readout integration within a large-scale colorcenter quantum computer.