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Proceedings of the National Academy of Sciences India Section A Physical Sciences

Hardware Implementation of an Efficient 32-bit Reversible Full Adder and its Analysis for Quantum applications

Gaganpreet Kaur, Khushpreet Singh, Rudraa Dadhich, Tanish Sadana, Nishant Mittal, Vanshika Garg, Ishaana Ali

Published Jun 27, 2026• 0 citations
Publisher
DOI
10.1007/s40010-026-01135-w

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Quantum computing is gaining importance as a promising approach for achieving energy-efficient and reliable computation, where reversible logic circuits play a key role. Full adders are fundamental components of arithmetic and logic units, and their correct operation is essential for overall system performance. With continued technology scaling, digital circuits are increasingly affected by manufacturing defects and permanent faults, making fault modeling and testability analysis critically important. Among various fault models, the stuck-at fault model is widely used due to its simplicity and its ability to represent common physical defects. This paper presents a detailed stuck-at fault analysis of a reversible full adder designed using Peres gates. The proposed architecture efficiently generates Sum and Carry outputs while reducing gate count and information loss. To evaluate practical feasibility, the full adder is implemented on the IBM quantum computing platform using IBM Composer and simulated through the Qiskit framework. Both fault-free and faulty conditions are examined by introducing stuck- at-0 and stuck-at-1 faults at key nodes affecting the Sum and Carry outputs. State-vector analysis, probability distributions, and measurement results are obtained for all possible input combinations. The exhaustive fault analysis achieves a fault coverage of 87.5% for both SA-0 and SA-1 conditions, indicating high fault observability. The results confirm that the proposed Peres gate–based reversible full adder is well suited for fault-tolerant arithmetic applications in reversible and quantum computing environments.