Design and fabrication of ion traps for low RF power dissipation
Jonathan David Sterk, Matthew G. Blain, Matthew A. Delaney, Raymond A. Haltli, E. Heller, Andrew Leeth Holterhoff, T. Jennings, N. Jimenez, O. Katz, Alexander E. Kozhanov, Zachary Meinelt, T P Morrison, Eric Ou, Jay Wesley Van Der Wall, Crystal Noel, Daniel Stick
Large surface-electrode ion traps with multiple trapping regions and junctions are a natural approach to scaling trapped ion quantum computers, supporting the connectivity and ion counts necessary for complex quantum algorithms. However, a major hurdle in this scaling is on-chip power dissipation from the applied RF voltage, which increases at a rate between linear and cubic relative to trap size, depending on whether the losses are dielectric or Ohmic. Here, we present two versions of a trap with features designed to reduce both types of RF power dissipation. The first variant contains a raised RF electrode that increases the electrode–ground distance to reduce capacitance. Different DC voltage sources are demonstrated on this trap to show that technical noise before the filter remains the dominant source of voltage noise and therefore motional heating. The second variant additionally includes a method for removing dielectric from beneath the RF electrode to further reduce dielectric losses. These traps were demonstrated at room temperature with 40Ca+ ions. The similar heating rates and heating rate axial frequency dependencies between 2.4 and 3.0 MHz illustrate that this dielectric modification is not detrimental to trap performance.
Large surface-electrode ion traps with multiple trapping regions and junctions are a natural approach to scaling trapped ion quantum computers, supporting the connectivity and ion counts necessary for complex quantum algorithms. However, a major hurdle in this scaling is on-chip power dissipation from the applied RF voltage, which increases at a rate between linear and cubic relative to trap size, depending on whether the losses are dielectric or Ohmic. Here, we present two versions of a trap with features designed to reduce both types of RF power dissipation. The first variant contains a raised RF electrode that increases the electrode–ground distance to reduce capacitance. Different DC voltage sources are demonstrated on this trap to show that technical noise before the filter remains the dominant source of voltage noise and therefore motional heating. The second variant additionally includes a method for removing dielectric from beneath the RF electrode to further reduce dielectric losses. These traps were demonstrated at room temperature with 40Ca+ ions. The similar heating rates and heating rate axial frequency dependencies between 2.4 and 3.0 MHz illustrate that this dielectric modification is not detrimental to trap performance.
Surface ion traps with two-dimensional layouts of trapping regions are natural architectures for storing large numbers of ions and supporting the connectivity needed to implement quantum algorithms. Many of the components and operations needed to fully exploit this architecture have already been demonstrated, including operation at cryogenic temperatures with low heating, low excitation transport, and ion control and detection with integrated photonics. Here we demonstrate a trap that addresses the scaling challenge of increasing power dissipation as the RF electrode increases in size. By raising the RF electrode and removing most of the insulating dielectric layer below it we reduce both ohmic and dielectric power dissipation. We also measure heating rates across a range of motional frequencies and for different voltage sources in a trap with a raised RF electrode but solid dielectric.
Abstract Ions in surface-electrode ion traps are susceptible to heating due to various noise sources, which can degrade coherence and fidelity. This study investigates the heating mechanisms in surface-electrode ion traps, with a focus on the role of dielectric materials and the effectiveness of shielding techniques. Using the fluctuation-dissipation theorem and finite element simulations, we demonstrate that a metallic shielding layer beneath the dielectric layer can reduce the heating rate by five orders of magnitude. Additionally, indenting the dielectric layer supporting the electrodes further decreases the heating rate by minimizing the exposed area in the ion’s field of view. Experimental results validate these findings, showing a three-order-of-magnitude reduction in heating rates for traps with a shielding layer. Our work provides a comprehensive methodology for assessing and minimizing dielectric heating, offering practical design insights for improving the performance of trapped ion quantum systems.
Microfabricated Paul ion traps show tremendous promise for large-scale quantum information processing. However, motional heating of ions can have a detrimental effect on the fidelity of quantum logic operations in miniaturized, scalable designs. In many experiments, motional heating rates are ascribed solely to anomalous heating, which arises at least in part from electric field noise from the trap surface not attributable to any known mechanisms. Contributions to measured ion heating rates due to technical voltage noise present on the static (DC) and radio frequency (RF) electrodes—i.e., due to voltage sources, amplifiers, and other electrical components—can often be overlooked. We present a reliable method for determining the extent to which motional heating is dominated by technical voltage noise on the DC or RF electrodes. Also, we demonstrate that stray DC electric fields can shift the ion position such that technical noise on the RF electrode can significantly contribute to the motional heating rate. After minimizing the pseudopotential gradient experienced by the ion induced by stray DC electric fields, the motional heating due to RF technical noise can be significantly reduced.
Surface electrode ion trap is highly promising for practical quantum computing due to its superior controllability on the trapped ions. With advanced microfabrication techniques, silicon has been developed as an ion trap substrate for delicate surface electrodes design and monolithic electro-optical components integration. However, the high RF loss of silicon hinders the possible large-scale implementation. In this work, we demonstrate a through silicon via (TSV) integrated ion trap, which has low RF loss due to the elimination of wire bonding (WB) pads on the surface and the miniaturization of form factor. We also fabricate two types of conventional WB traps with or without a grounding screen layer. The RF performances of different ion traps are tested and compared, in terms of on-chip S-parameter, postpackaging resonance, and resulting power loss. The results show that the TSV trap has low S21 (~0.2 dB at 50 MHz), highQfactor (~22), and low power loss (0.26 W) compared to WB traps. In addition, 3-D finite element modeling (FEM) is employed for electric field visualization and RF loss analysis of different traps. The extracted results from the modeling show a decent agreement with the measurements. In addition to various RF tests, the design, fabrication, and ion trapping operation of different ion traps are presented. This work provides insights into RF loss of ion trapping devices and offers a new solution for RF loss reduction.
Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. In such context, this thesis is committed to boost the scalability of ion trap by integrating advanced 3D interconnects (e.g., through silicon via) and other functional modules (e.g., silicon photonics and multilayer metallization). 3D interconnects are integrated in the half space underneath surface electrode, to replace conventional wire bonding that extends out of the surface. Silicon photonics (grating coupler and waveguide) in place of bulk optics and lenses are used for on-chip light routing and emission. Multilayer metallization is used to maintain the overall RF performance and enable high-density interconnection where necessary. Firstly, surface electrode ion traps on different substrates (namely high resistivity silicon, silicon with grounding plane and glass) are designed and fabricated. Standard CMOS back-end-of-line fabrication process on 12-inch wafer platform is employed. The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. Due to the incorporation of TSV, the original wire bonding pads as well as the connection circuits on the surface electrodes can be eliminated. As a result, the form factor of TSV integrated trap is reduced by ~10 times. Correspondingly, the parasitic capacitance between neighboring electrodes is reduced from >24 pF to 3 pF. Similarly, the insertion loss of TSV integrated trap drops to 0.11 dB, in sharp comparison to the previous traps on silicon substrates (up to 2.4 dB). Analytical models are built to respectively characterize the electrode capacitance and overall power loss, and a good agreement is achieved between the model and the measurement result. In addition, since TSV is located in the half space underneath the surface electrodes, the electrodes geometry design is enabled with high flexibility. Meanwhile, the laser obstruction issue due to the stick-out bonding wires has been resolved. In terms of the ion trapping performance, both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and the lifetime (~30 minutes) of TSV trap are comparable with non-cryogenic traps of similar dimensions. Moreover, a customized CPGA with patterned redistribution layer is used to locate TSV integrated trap directly in the absence of glass interposer, facilitating high-efficiency thermal management and upgrading the packaging flexibility. At the next stage, the co-integration of other functional modules such as silicon photonics and multilayer metallization with TSV trap is investigated. In silicon photonics module, waveguide and grating coupler are on-chip introduced in place of bulk optics to achieve localized light routing and emission. In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. The deviation between the simulation and measurement is largely due to the fabrication imperfection and the resultant sloped grating coupler profile. This thesis focuses on the scalability enhancement of ion trap by integrating TSV, silicon photonics and multilayer metallization into conventional ion trap. The results are promising and pave the way for the future large scale quantum computing based on trapped ion.
Abstract Scaling trapped-ion quantum computing will require robust trapping of at least hundreds of ions over long periods, while increasing the complexity and functionality of the trap itself. Symmetric three-dimensional (3D) structures enable high trap depth, but microfabrication techniques are generally better suited to planar structures that produce less ideal conditions for trapping. We present an ion trap fabricated on stacked eight-inch wafers in a large-scale micro-electro-mechanical system microfabrication process that provides reproducible traps at a large volume. Electrodes are patterned on the surfaces of two opposing wafers bonded to a spacer, forming a 3D structure with 2.5 μm standard deviation in alignment across the stack. We implement a design achieving a trap depth of 1 eV for a 40Ca+ ion held at 200 μm from either electrode plane. We characterize traps, achieving measurement agreement with simulations to within ±5% for mode frequencies spanning 0.6–3.8 MHz, and evaluate stray electric field across multiple trapping sites. We measure motional heating rates over an extensive range of trap frequencies, and temperatures, observing 40 phonons/s at 1 MHz and 185 K. This fabrication method provides a highly scalable approach for producing a new generation of 3D ion traps.