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ICTACT Journal on Communication Technology

REVIEW ON CONSTRUCTION METHODS FOR REGULAR AND NON-QUASI CYCLIC LDPC CODES

S Vengatesh Kumar

Published Sep 1, 2019• 0 citations
Publisher

Abstract

Low Density Parity Check (LDPC) codes are one of the most powerful error correction codes available today. Its Shannon capability that closely matches performance and lower decoding complexity has made them the best choice for many wired and wireless applications. This Paper provides an overview of the LDPC codes and compares the Gallager method, the Reed-Solomon-based algebraic method, and the combinatorial Progressive Growth (PEG) method for constructing regular LDPC codes and also Overlapped and Modified overlapped message passing algorithm for Non-Quasi Cyclic(NQC) LDPC codes.

DOI
10.21917/ijct.2019.0298

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Low Density Parity Check (LDPC) codes are one of the most powerful error correction codes available today. Its Shannon capability that closely matches performance and lower decoding complexity has made them the best choice for many wired and wireless applications. This Paper provides an overview of the LDPC codes and compares the Gallager method, the Reed-Solomon-based algebraic method, and the combinatorial Progressive Growth (PEG) method for constructing regular LDPC codes and also Overlapped and Modified overlapped message passing algorithm for Non-Quasi Cyclic(NQC) LDPC codes.
In this paper, we present three construction methods of systematic regular LDPC-CCs based on randomly or algebraically structured sparse matrices. We provide an overview of LDPC-CCs and compares between Gallager’s, Mackay-Neal and Quasi-Cyclic (QC) construction methods, which are a good choice for many wireless applications due to their errors correction efficiency and low decoding complexity. At a rate-1/2, for the same size of the parity matrix to obtain the same encoding and decoding complexity, and using the Bit Flipping (BF) decoding algorithm over Additive White Gaussian Noise (AWGN) channel, we simulated the BER performance of a (3,6) regular LDPC convolutional codes, where the results showed that Gallager’s construction method (random) outperforms Mackay-Neal and QC ones.
Progressive Edge-Growth(PEG) algorithm is a method for constructing Low Density Parity-Check(LDPC) codes based on Tanner graph.Studies show that LDPC codes constructed with the algorithm can achieve excellent error-correcting performance.Based on the algorithm,the Quasi-Cyclic(QC) LDPC codes are proposed in this paper and simulations show that the QC-LDPC codes have almost the same excellent performance as the random codes constructed with the PEG algorithm.In addition,these codes have the property of quasi-cyclic structure,and the encoding and decoding can be implemented with simple shift registers.Besides,the code rates of the LDPC codes constructed with the proposed algorithm are more flexible to be adjusted.
Low density parity check (LDPC) codes are capacity-approaching codes, which means that practical constructions exist that allow the noise threshold to be set very close to the theoretical Shannon limit for a memory less channel. LDPC codes are finding increasing use in applications like LTE-Networks, digital television, high density data storage systems, deep space communication systems etc. Several algebraic and combinatorial methods are available for constructing LDPC codes. In this paper we discuss a novel low complexity algebraic method for constructing regular LDPC like codes derived from full rank codes. We demonstrate that by employing these codes over AWGN channels, coding gains in excess of 2dB over un-coded systems can be realized when soft iterative decoding using a parity check tree is employed.
Low-density parity-check (LDPC) codes have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost, time, power and bandwidth requirements of target applications. The constructed codes should also meet error rate performance requirements of those applications. Since their rediscovery, there has been much research work on LDPC code construction and implementation. LDPC codes can be designed over a wide space with parameters such as girth, rate and length. There is no unique method of constructing LDPC codes. Existing construction methods are limited in some way in producing good error correcting performing and easily implementable codes for a given rate and length. There is a need to develop methods of constructing codes over a wide range of rates and lengths with good performance and ease of hardware implementability. LDPC code hardware design and implementation depend on the structure of target LDPC code and is also as varied as LDPC matrix designs and constructions. There are several factors to be considered including decoding algorithm computations,processing nodes interconnection network, number of processing nodes, amount of memory, number of quantization bits and decoding delay. All of these issues can be handled in several different ways. \nThis thesis is about construction of LDPC codes and their hardware implementation. LDPC code construction and implementation issues mentioned above are too many to be addressed in one thesis. The main contribution of this thesis is the development of LDPC code construction methods for some classes of structured LDPC codes and techniques for reducing decoding time. We introduce two main methods for constructing structured codes. In the first method, column-weight two LDPC codes are derived from distance graphs. A wide range of girths, rates and lengths are obtained compared to existing methods. The performance and implementation complexity of obtained codes depends on the structure of their corresponding distance graphs. In the second method, a search algorithm based on bit-filing and progressive-edge growth algorithms is introduced for constructing quasi-cyclic LDPC codes. The algorithm can be used to form a distance or Tanner graph of a code. This method could also obtain codes over a wide range of parameters. Cycles of length four are avoided by observing the row-column constraint. \nRow-column connections observing this condition are searched sequentially or randomly. Although the girth conditions are not sufficient beyond six, larger girths codes were easily obtained especially at low rates. The advantage of this algorithm compared to other methods is its flexibility. It could be used to construct codes for a given rate and length with girths of at least six for any sub-matrix configuration or rearrangement. The code size is also easily varied by increasing or decreasing sub-matrix size. Codes obtained using a sequential search criteria show poor performance at low girths (6 and 8) while random searches result in good performing codes. \nQuasi-cyclic codes could be implemented in a variety of decoder architectures. One of the many options is the choice of processing nodes interconnect. We show how quasi-cyclic codes processing could be scheduled through a multistage network. Although these net-works have more delay than other modes of communication, they offer more flexibility at a reasonable cost. Banyan and Benes networks are suggested as the most suitable networks. \nDecoding delay is also one of several issues considered in decoder design and implementation. In this thesis, we overlap check and variable node computations to reduce decoding time. Three techniques are discussed, two of which are introduced in this thesis. The techniques are code matrix permutation, matrix space restriction and sub-matrix row-column scheduling. Matrix permutation rearranges the parity-check matrix such that rows and columns that do not have connections in common are separated. This techniques can be applied to any matrix. Its effectiveness largely depends on the structure of the code. We show that its success also depends on the size of row and column weights. Matrix space restriction is another technique that can be applied to any code and has fixed reduction in time or amount of overlap. Its success depends on the amount of restriction and may be traded with performance loss. The third technique already suggested in literature relies on the internal cyclic structure of sub-matrices to achieve overlapping. The technique is limited to LDPC code matrices in which the number of sub-matrices is equal to row and column weights. We show that it can be applied to other codes with a lager number of sub-matrices than code weights. However, in this case maximum overlap is not guaranteed. We calculate the lower bound on the amount of overlapping. Overlapping could be applied to any sub-matrix configuration of quasi-cyclic codes by arbitrarily choosing \nthe starting rows for processing. Overlapping decoding time depends on inter-iteration waiting times. We show that there are upper bounds on waiting times which depend on the code weights. Waiting times could be further reduced by restricting shifts in identity sub-matrices or using smaller sub-matrices. This overlapping technique can reduce the decoding time by up to 50% compared to conventional message and computation scheduling. \nTechniques of matrix permutation and space restriction results in decoder architectures that are flexible in LDPC code design in terms of code weights and size. This is due to the fact that with these techniques, rows and columns are processed in sequential order to achieve overlapping. However, in the existing technique, all sub-matrices have to be processed in parallel to achieve overlapping. Parallel processing of all code sub-matrices requires the architecture to have the number of processing units at least equal to the number sub-matrices. Processing units and memory space should therefore be distributed among the sub-matrices according to the sub-matrices arrangement. This leads to high complexity or inflexibility in the decoder architecture. We propose a simple, programmable and high throughput decoder architecture based on matrix permutation and space restriction techniques.
A novel construction for quasi-cyclic (QC) regular and irregular low-density parity-check (LDPC) codes based on a modification of the QC Progressive Edge Growth (PEG) algorithm is presented. Edge placement of the PEG-based algorithm is enhanced by use of the sum-product algorithm in the design of the parity-check matrix. The proposed algorithm is highly flexible in block length and rate, in particular when compared with algebraic constructions. The codes constructed by the proposed methods are tested in the AWGN channel and performance improvements are achieved. The proposed QC-LDPC codes provide an inherent trade-off between code performance and encoding/decoding complexity.