Large-scale, fault-tolerant quantum computing requires the integration of a substantial number of quantum bits (qubits). Efficient readout of these qubits depends on the underlying technology but invariably calls for scalable multiplexed schemes. This paper introduces a novel digital code multiplexing approach for charge readout in quantum computing. Operating entirely at digital levels, the proposed scheme eliminates the need for complex waveform or sinusoidal signal generation. Unlike conventional reflectometry, where the number of qubits dictates the number of physical resonant circuits, our method only influences the digital clock frequency, enabling a more compact and scalable implementation. We demonstrate this scheme by modulating two industrial single-electron transistors (SETs) through a transimpedance amplifier (TIA)-based readout chain operating at 4.2~K. Experimental results show that the proposed method reliably distinguishes SET conductivity states under multiplexing, achieving a bit-error rate (BER) below $10^{-3}$ within an integration time of $4.55~\mu$s.
Large-scale, fault-tolerant quantum computing requires the integration of a substantial number of quantum bits (qubits). Efficient readout of these qubits depends on the underlying technology but invariably calls for scalable multiplexed schemes. This paper introduces a novel digital code multiplexing approach for charge readout in quantum computing. Operating entirely at digital levels, the proposed scheme eliminates the need for complex waveform or sinusoidal signal generation. Unlike conventional reflectometry, where the number of qubits dictates the number of physical resonant circuits, our method only influences the digital clock frequency, enabling a more compact and scalable implementation. We demonstrate this scheme by modulating two industrial single-electron transistors (SETs) through a transimpedance amplifier (TIA)-based readout chain operating at 4.2~K. Experimental results show that the proposed method reliably distinguishes SET conductivity states under multiplexing, achieving a bit-error rate (BER) below 10−3 within an integration time of 4.55μs.
Spin qubits are a promising candidate for large-scale fault-tolerant quantum computing due to2footprint per qubit, higher operating temperature (up to 1K [1]) and possible compatibility with industrial CMOS processes [2], [3]. However, the need for a simultaneous ~µs readout of thousands of devices is especially challenging in terms of power consumption and footprint per qubit [4], [5]. Frequency-domain multiplexed (FDM) reflectometry architectures using cryo-CMOS have been introduced in [6], [7], [8] but these circuits require bulky > 100µm2inductors and do not match readout time specifications using actual quantum devices. Besides, current integrator readout schemes have been proposed [9], [10], but offer no scaling perspectives beyond time-domain multiplexing, leading to strong constraints in terms of bandwidth and power consumption. Recently, [4] introduced a capacitive-feedback transimpedance amplifier achieving an inductor-less FDM readout of two quantum dots [11]. Nevertheless, the demonstrated power consumption per qubit of 214µW/qubit remains too high to match the maximum heat dissipation allowed near quantum devices [12] in a large-scale perspective. Moreover, the used On-Off Keying (OOK) modulations are limited to one qubit per carrier, thus requiring high bandwidth and power consumption in order to read thousands of qubits.
Quantum computing is predicted to provide unprecedented enhancements in computational power. A quantum computer requires implementation of a well-defined and controlled quantum system of many interconnected qubits, each defined using fragile quantum states. The interest in a spin-based quantum computer in silicon stems from demonstrations of very long spin-coherence times, high-fidelity single spin control and compatibility with industrial mass-fabrication. Industrial scale fabrication of the silicon platform offers a clear route towards a large-scale quantum computer, however, some of the processes and techniques employed in qubit demonstrators are incompatible with a dense and foundry-fabricated architecture. In particular, spin-readout utilises external sensors that require nearly the same footprint as qubit devices. In this thesis, improved readout techniques for silicon quantum devices are presented and routes towards implementation of a scalable and high-sensitivity readout architecture are investigated. Firstly, readout sensitivity of compact gate-based sensors is improved using a high-quality factor resonator and Josephson parametric amplifier that are fabricated separately from quantum dots. Secondly, an integrated transistor-based control circuit is presented using which sequential readout of two quantum dot devices using the same gate-based sensor is achieved. Finally, a large-scale readout architecture based on random-access and frequency multiplexing is introduced. The impact of readout circuit footprint on readout sensitivity is determined, showing routes towards integration of conventional circuits with quantum devices in a dense architecture, and a fault-tolerant architecture based on mediated exchange is introduced, capable of relaxing the limitations on available control circuit footprint per qubit. Demonstrations are based on foundry-fabricated transistors and few-electron quantum dots, showing that industry fabrication is a viable route towards quantum computation at a scale large enough to begin addressing the most challenging computational problems.
Single electron transistors (SETs) are nanoscale electrometers of unprecedented sensitivity, and as such have been proposed as readout devices in a number of quantum computer architectures. The authors show that the functionality of a standard SET can be multiplexed so as to operate as both readout device and control gate for solid-state qubit systems based on charge localization and spin-charge transduction. Such multiplexing offers new possibilities for gate density reduction in nanoscale devices, and may therefore play a role in scalable quantum computer architectures.
High-fidelity qubit readout is critical in order to obtain the thresholds needed to implement quantum error-correction protocols and achieve fault-tolerant quantum computing. Large-scale silicon qubit devices will have densely packed arrays of quantum dots with multiple charge sensors that are, on average, farther away from the quantum dots, entailing a reduction in readout fidelities. Here, we present a readout technique that enhances the readout fidelity in a linear SiMOS four-dot array by amplifying correlations between a pair of single-electron transistors, known as a twin SET. By recording and subsequently correlating the twin SET traces as we modulate the dot detuning across a charge transition, we demonstrate a reduction in the charge readout infidelity by over one order of magnitude compared to traditional readout methods. We also study the spin-to-charge conversion errors introduced by the modulation technique and conclude that faster modulation frequencies avoid relaxation-induced errors without introducing significant spin-flip errors, favoring the use of the technique at short integration times. This method not only allows for faster and higher-fidelity qubit measurements but it also enhances the signal corresponding to charge transitions that take place farther away from the sensors, enabling a way to circumvent the reduction in readout fidelities in large arrays of qubits. Published by the American Physical Society 2024
Semiconductor quantum dot arrays are a promising platform to perform spin-based error-corrected quantum computation with large numbers of qubits. However, due to the diverging number of possible charge configurations combined with the limited sensitivity of large-footprint charge sensors, achieving single-spin occupancy in each dot in a growing quantum dot array is exceedingly complex. Therefore, to scale-up a spin-based architecture we must change how individual charges are readout and controlled. Here, we demonstrate single-spin occupancy of each dot in a foundry-fabricated array by combining two methods. 1/ Loading a finite number of electrons into the quantum dot array; simplifying electrostatic tuning by isolating the array from the reservoirs. 2/ Deploying multiplex gate-based reflectometry to dispersively probe charge tunneling and spin states without charge sensors or reservoirs. Our isolated arrays probed by embedded multiplex readout can be readily electrostatically tuned. They are thus a viable, scalable approach for spin-based quantum architectures. Large-footprint, low-sensitivity charge sensors hinder scaling semiconductor quantum dot arrays for quantum computation. Here the authors present a potentially scalable approach using multiplexed gate-based readout and operation in a foundry-fabricated quantum dot array, demonstrating single-electron occupancy.
This paper presents extensive guidelines for the design of an integrated DC-readout interface for semiconductor spin qubits. Since the focus is on the readout via a single electron transistor (SET), the SET behavior and performance are first described and modeled, showing that the signal-to-noise ratio (SNR) theoretically achievable by a SET-based DC-readout is significantly beyond the state-of-the-art. Practical circuit architectures for implementing a DC-readout, such as the voltage amplifier, the transimpedance amplifier, the charge sampling, and the current pre-amplifier, are then analyzed by deriving their design equations and trade-offs. As a result, the practical performances of those different solutions are evaluated and compared, thus presenting clear selection criteria for the readout architecture and its design equations given the specific parameters of the SET sensor.