Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Circuits and Systems I Regular Papers

DC-Readout of Semiconductor Spin Qubits: Opportunities and Limits

Gerd Kiene, Oriol Pietx-Casas, Masoud Babaie, Lieven M. K. Vandersypen, Fabio Sebastiano

Published Feb 19, 2025• 5 citations
Publisher

Abstract

This paper presents extensive guidelines for the design of an integrated DC-readout interface for semiconductor spin qubits. Since the focus is on the readout via a single electron transistor (SET), the SET behavior and performance are first described and modeled, showing that the signal-to-noise ratio (SNR) theoretically achievable by a SET-based DC-readout is significantly beyond the state-of-the-art. Practical circuit architectures for implementing a DC-readout, such as the voltage amplifier, the transimpedance amplifier, the charge sampling, and the current pre-amplifier, are then analyzed by deriving their design equations and trade-offs. As a result, the practical performances of those different solutions are evaluated and compared, thus presenting clear selection criteria for the readout architecture and its design equations given the specific parameters of the SET sensor.

DOI
10.1109/tcsi.2025.3542335

Related papers

Modeling and Experimental Validation of the Intrinsic SNR in Spin Qubit Gate-Based Readout and Its Impacts on Readout Electronics

Bagas Prabowo, Jurgen Dijkema, Xiao Xue +3 more

In semiconductor spin quantum bits (qubits), the radio-frequency (RF) gate-based readout is a promising solution for future large-scale integration, as it allows for a fast, frequency-multiplexed readout architecture, enabling multiple qubits to be read out simultaneously. This paper introduces a theoretical framework to evaluate the effect of various parameters, such as the readout probe power, readout chain's noise performance, and integration time on the intrinsic readout signal-to-noise ratio (SNR), and thus readout fidelity of RF gate-based readout systems. By analyzing the underlying physics of spin qubits during readout, this work proposes a qubit readout model that takes into account the qubit's quantum mechanical properties, providing a way to evaluate the trade-offs among the aforementioned parameters. The validity of the proposed model is evaluated by comparing the simulation and experimental results. The proposed analytical approach, the developed model, and the experimental results enable designers to optimize the entire readout chain effectively, thus leading to a faster, lower-power readout system with integrated cryogenic electronics.

arXiv:2312.08993•IEEE Transactions on Quantum Engineering•Jan 1, 2024•6 citations

Modelling single-electron-transistor-based readout in the Kane solid-state quantum computer

Chris I. Pakes, Vincent I. Conrad, J C Ang +5 more

The Kane (Kane B E 1998 Nature 393 133) solid-state quantum computer aims to exploit as qubits an array of 31 P nuclear spins embedded in a silicon matrix. A proposed scheme for readout of a qubit spin state relies on measurement of the associated spin state of its donor electron, by attempting to induce and detect, using a single-electron transistor (SET), spin-polarized motion of the electron to an adjacent donor site. The sensitivity required of a SET for detection of sub-surface electronic charge motion in a MOS architecture is examined by simulation of the capacitive coupling of the buried charge to the SET device. It is shown that the SET can support readout of the qubit electronic charge states within the appropriate electron spin relaxation time. This paper presents a novel application of Technology Computer Aided Design, which presents itself as a valuable tool for the design of nanoscale device architectures employing precision electrometry for readout of quantum logic states.

Nanotechnology•Jan 10, 2003•5 citations

Analysis on Noise Requirements of RF Front-End Circuits for Spin Qubit Readout

Yatao Peng, Andrea Ruffino, Edoardo Charbon A

Currently, radio frequency (RF) measurement setups for semiconductor qubits are implemented with high performance discrete devices operating at cryogenic temperatures, and the output signals are detected by room temperature instruments.This is impractical for a real quantum processor, and integrated circuits (ICs) should be designed for spin qubit readout in a practical quantum computer, to ensure system reliability and compactness.To guide the system-level IC design, we analyze in this work noise specifications of RF front-end circuits for qubit readout, mainly focusing on noise figure (NF) of the lownoise-amplifier (LNA) and phase noise (PN) of the voltage-controlled-oscillator (VCO).RF reflectometry and RF dispersive gate sensing (DGS) are two main spin qubit readout techniques, both of which should detect weak reflected signals as low as -135 dBm and distinguish <1% amplitude or phase variation, which results in high sensitivity and low noise requirements for the readout circuits, to achieve the high measurement fidelity.For the analysis, we model the RF reflectometry and RF-DGS as demodulators respectively of the on-off keying (OOK) signal and phase modulated (PM) signal from qubits.From this, we provide a first estimation of the required NF and PN for a given fidelity and readout bandwidth, as well as an insight into the relationship between phase resolution of RF-DGS and performance degradation due to PN of the VCO.We then review some state-of-the-art CMOS LNA and VCO topologies, which can be utilized in the spin qubit readout ICs to satisfy the specifications.

International Conference on Noise and Fluctuations•Aug 22, 2019•0 citations

A High-Sensitivity Charge Sensor for Silicon Qubits above 1 K

Jonathan Y. Huang, Wee Han Lim, Ross C. C. Leon +6 more

Recent studies of silicon spin qubits at temperatures above 1 K are encouraging demonstrations that the cooling requirements for solid-state quantum computing can be considerably relaxed. However, qubit readout mechanisms that rely on charge sensing with a single-island single-electron transistor (SISET) quickly lose sensitivity due to thermal broadening of the electron distribution in the reservoirs. Here we exploit the tunneling between two quantized states in a double-island single-electron transistor (SET) to demonstrate a charge sensor with an improvement in the signal-to-noise ratio by an order of magnitude compared to a standard SISET, and a single-shot charge readout fidelity above 99% up to 8 K at a bandwidth greater than 100 kHz. These improvements are consistent with our theoretical modeling of the temperature-dependent current transport for both types of SETs. With minor additional hardware overhead, these sensors can be integrated into existing qubit architectures for a high-fidelity charge readout at few-kelvin temperatures.

arXiv:2103.06433•Nano Letters•May 17, 2021•14 citations

Charge-Based Single-Shot Readout Systems in Quantum Computing

Conor Power, Robert Bogdan Staszewski, Elena Blokhina

Measurement of a qubit (quantum bit) is a key element of quantum computation and is necessary for extracting information from a quantum processor. The physical implementation of a measurement protocol involves monitoring a physical quantity of a sensor, such as a current or a voltage, that is correlated with the state of the qubit to be measured. The monitoring of these sensors used to measure qubits in modern quantum computer architectures is typically divided between RF reflectometry and current/voltage monitoring. There are tradeoffs involved with both approaches for the reliable and accurate readout of qubits when it comes to scalable quantum computing architectures. In this article, we will review the working principles of a selection of sensors that are used to measure the state of qubits in semiconductors. The goal is to introduce electronic engineers with little or no background in quantum computing to the working principles of charge sensors in semiconductor quantum computers, their identification in various physical systems, and an overview of their design tradeoffs when measuring a qubit. This will allow electronic engineers to begin working with physics literature in the field of charge sensing. An overview of the article and the topics that will be discussed is given in Fig. 5.

•Nov 27, 2024•0 citations

Device/circuit simulations of silicon spin qubits based on a gate-all-around transistor

Tetsufumi Tanamoto, Keiji Ono

We theoretically investigated the readout process of a spin--qubit structure based on a gate-all-around (GAA) transistor. Our study focuses on a logical qubit composed of two physical qubits. Different spin configurations result in different charge distributions, which subsequently influence the electrostatic effects on the GAA transistor. Consequently, the current flowing through the GAA transistor depends on the qubit's state. We calculated the current-voltage characteristics of the three-dimensional configurations of the qubit and GAA structures, using technology computer-aided design (TCAD) simulations. Moreover, we performed circuit simulations using the Simulation Program with Integrated Circuit Emphasis (SPICE) to investigate whether a readout circuit made from complementary metal--oxide semiconductor (CMOS) transistors can amplify the weak signals generated by the qubits. Our findings indicate that, by dynamically controlling the applied voltage within a properly designed circuit, the readout can be detected effectively based on a conventional sense amplifier.

cond-mat.mes-hallCross-listedarXiv:2512.08152•Dec 10, 2025
This paper presents extensive guidelines for the design of an integrated DC-readout interface for semiconductor spin qubits. Since the focus is on the readout via a single electron transistor (SET), the SET behavior and performance are first described and modeled, showing that the signal-to-noise ratio (SNR) theoretically achievable by a SET-based DC-readout is significantly beyond the state-of-the-art. Practical circuit architectures for implementing a DC-readout, such as the voltage amplifier, the transimpedance amplifier, the charge sampling, and the current pre-amplifier, are then analyzed by deriving their design equations and trade-offs. As a result, the practical performances of those different solutions are evaluated and compared, thus presenting clear selection criteria for the readout architecture and its design equations given the specific parameters of the SET sensor.
In semiconductor spin quantum bits (qubits), the radio-frequency (RF) gate-based readout is a promising solution for future large-scale integration, as it allows for a fast, frequency-multiplexed readout architecture, enabling multiple qubits to be read out simultaneously. This paper introduces a theoretical framework to evaluate the effect of various parameters, such as the readout probe power, readout chain's noise performance, and integration time on the intrinsic readout signal-to-noise ratio (SNR), and thus readout fidelity of RF gate-based readout systems. By analyzing the underlying physics of spin qubits during readout, this work proposes a qubit readout model that takes into account the qubit's quantum mechanical properties, providing a way to evaluate the trade-offs among the aforementioned parameters. The validity of the proposed model is evaluated by comparing the simulation and experimental results. The proposed analytical approach, the developed model, and the experimental results enable designers to optimize the entire readout chain effectively, thus leading to a faster, lower-power readout system with integrated cryogenic electronics.
The Kane (Kane B E 1998 Nature 393 133) solid-state quantum computer aims to exploit as qubits an array of 31 P nuclear spins embedded in a silicon matrix. A proposed scheme for readout of a qubit spin state relies on measurement of the associated spin state of its donor electron, by attempting to induce and detect, using a single-electron transistor (SET), spin-polarized motion of the electron to an adjacent donor site. The sensitivity required of a SET for detection of sub-surface electronic charge motion in a MOS architecture is examined by simulation of the capacitive coupling of the buried charge to the SET device. It is shown that the SET can support readout of the qubit electronic charge states within the appropriate electron spin relaxation time. This paper presents a novel application of Technology Computer Aided Design, which presents itself as a valuable tool for the design of nanoscale device architectures employing precision electrometry for readout of quantum logic states.
Currently, radio frequency (RF) measurement setups for semiconductor qubits are implemented with high performance discrete devices operating at cryogenic temperatures, and the output signals are detected by room temperature instruments.This is impractical for a real quantum processor, and integrated circuits (ICs) should be designed for spin qubit readout in a practical quantum computer, to ensure system reliability and compactness.To guide the system-level IC design, we analyze in this work noise specifications of RF front-end circuits for qubit readout, mainly focusing on noise figure (NF) of the lownoise-amplifier (LNA) and phase noise (PN) of the voltage-controlled-oscillator (VCO).RF reflectometry and RF dispersive gate sensing (DGS) are two main spin qubit readout techniques, both of which should detect weak reflected signals as low as -135 dBm and distinguish <1% amplitude or phase variation, which results in high sensitivity and low noise requirements for the readout circuits, to achieve the high measurement fidelity.For the analysis, we model the RF reflectometry and RF-DGS as demodulators respectively of the on-off keying (OOK) signal and phase modulated (PM) signal from qubits.From this, we provide a first estimation of the required NF and PN for a given fidelity and readout bandwidth, as well as an insight into the relationship between phase resolution of RF-DGS and performance degradation due to PN of the VCO.We then review some state-of-the-art CMOS LNA and VCO topologies, which can be utilized in the spin qubit readout ICs to satisfy the specifications.
Recent studies of silicon spin qubits at temperatures above 1 K are encouraging demonstrations that the cooling requirements for solid-state quantum computing can be considerably relaxed. However, qubit readout mechanisms that rely on charge sensing with a single-island single-electron transistor (SISET) quickly lose sensitivity due to thermal broadening of the electron distribution in the reservoirs. Here we exploit the tunneling between two quantized states in a double-island single-electron transistor (SET) to demonstrate a charge sensor with an improvement in the signal-to-noise ratio by an order of magnitude compared to a standard SISET, and a single-shot charge readout fidelity above 99% up to 8 K at a bandwidth greater than 100 kHz. These improvements are consistent with our theoretical modeling of the temperature-dependent current transport for both types of SETs. With minor additional hardware overhead, these sensors can be integrated into existing qubit architectures for a high-fidelity charge readout at few-kelvin temperatures.
Measurement of a qubit (quantum bit) is a key element of quantum computation and is necessary for extracting information from a quantum processor. The physical implementation of a measurement protocol involves monitoring a physical quantity of a sensor, such as a current or a voltage, that is correlated with the state of the qubit to be measured. The monitoring of these sensors used to measure qubits in modern quantum computer architectures is typically divided between RF reflectometry and current/voltage monitoring. There are tradeoffs involved with both approaches for the reliable and accurate readout of qubits when it comes to scalable quantum computing architectures. In this article, we will review the working principles of a selection of sensors that are used to measure the state of qubits in semiconductors. The goal is to introduce electronic engineers with little or no background in quantum computing to the working principles of charge sensors in semiconductor quantum computers, their identification in various physical systems, and an overview of their design tradeoffs when measuring a qubit. This will allow electronic engineers to begin working with physics literature in the field of charge sensing. An overview of the article and the topics that will be discussed is given in Fig. 5.
We theoretically investigated the readout process of a spin--qubit structure based on a gate-all-around (GAA) transistor. Our study focuses on a logical qubit composed of two physical qubits. Different spin configurations result in different charge distributions, which subsequently influence the electrostatic effects on the GAA transistor. Consequently, the current flowing through the GAA transistor depends on the qubit's state. We calculated the current-voltage characteristics of the three-dimensional configurations of the qubit and GAA structures, using technology computer-aided design (TCAD) simulations. Moreover, we performed circuit simulations using the Simulation Program with Integrated Circuit Emphasis (SPICE) to investigate whether a readout circuit made from complementary metal--oxide semiconductor (CMOS) transistors can amplify the weak signals generated by the qubits. Our findings indicate that, by dynamically controlling the applied voltage within a properly designed circuit, the readout can be detected effectively based on a conventional sense amplifier.