This preprint reports a bounded IBM Heron hardware observation of parity-sector and excitation-number correlated decoherence asymmetry in small XY-Hamiltonian circuits. The dynamical Lie algebra of the XY Hamiltonian decomposes under the parity operator, and the experiment measures parity leakage rates across labelled sectors without promoting the observation as a DLA-only causal effect. The archived study uses a 342-circuit campaign on IBM ibm_kingston (Heron r2, 156 qubits), with n = 4 circuits across eight Trotter depths. It reports an odd-sector leakage excess over the even sector, with seven of eight tested depths individually significant under Welch tests, while explicitly treating shared-qubit and shared-calibration context as a boundary on inference. The record includes the manuscript source and PDF for a reproducible archival preprint. Claims are limited to the named hardware campaign, committed raw-count artefacts, stated reducers, and the open repository at https://github.com/anulum/scpn-quantum-control.
This preprint reports a bounded IBM Heron hardware observation of parity-sector and excitation-number correlated decoherence asymmetry in small XY-Hamiltonian circuits. The dynamical Lie algebra of the XY Hamiltonian decomposes under the parity operator, and the experiment measures parity leakage rates across labelled sectors without promoting the observation as a DLA-only causal effect. The archived study uses a 342-circuit campaign on IBM ibm_kingston (Heron r2, 156 qubits), with n = 4 circuits across eight Trotter depths. It reports an odd-sector leakage excess over the even sector, with seven of eight tested depths individually significant under Welch tests, while explicitly treating shared-qubit and shared-calibration context as a boundary on inference. The record includes the manuscript source and PDF for a reproducible archival preprint. Claims are limited to the named hardware campaign, committed raw-count artefacts, stated reducers, and the open repository at https://github.com/anulum/scpn-quantum-control.
This preprint reports a cost-bounded reduced-Pauli entanglement and tomography check for promoted Phase 3 DLA-parity and Fisher-information-modified Kuramoto--XY circuit families. The purpose is to distinguish parity-sector leakage structure from layout, prepared-state, and readout artefacts in small superconducting-hardware experiments. The archived IBM execution used physical qubits [1,2,3,4] on ibm_marrakesh, 162 main circuits, four readout-calibration circuits, 2048 shots per main circuit, and 8192 shots per readout circuit. A preregistered reducer produced 54 observable rows; the manuscript reports measured-minus-exact deviations, identifies the largest transverse two-qubit correlator deviations, and compares readout-mitigated replay and same-day ibm_fez replication. The record includes manuscript source, bibliography, and PDF. The claim boundary is hardware-observation and artefact-reduction evidence for these named circuit families, not a backend-independent universal promotion.
We report five preregistered experiments on the IQM Garnet 20-qubit square-lattice processor, each with its decision rule committed before any hardware data existed and each reported regardless of outcome. First, the even-over-odd parity-sector leakage asymmetry previously measured on IBM Heron r2 replicates on Garnet at preregistered power (relative asymmetry +0.068, one-sided p = 1.1 × 10−5). Because the noiseless parity leakage of these number-conserving XY-Trotter circuits is exactly zero, this is a statement about device noise. Second, the asymmetry is not stable: over ten execution windows it varies beyond shot noise at fixed depth (Cochran Q = 19.01 on 9 degrees of freedom, p = 0.025), more strongly when windows are pooled by provider calibration set (p = 0.0083), and an isolated sign reversal at depth 10 does not replicate. Third, a confirmatory campaign that takes the calibration epoch as its independent unit — twelve epochs, 688,128 shots — finds the asymmetry larger at depth 8 than at depth 12 (mean contrast +0.0173, one-sided p = 0.026); the lower bound is +0.0030 and three of twelve epochs have the opposite sign. Fourth, a calibration-aware layout optimiser developed on heavy-hex devices fails its frozen transfer rule: it is better than automatic placement at chain lengths 8 and 16 and worse at 12, and a powered follow-up confirms the reversal. All preregistrations, calibration snapshots, job identifiers, raw counts and analysis scripts are public. All quantum-hardware results were obtained on IQM Garnet through IQM Resonance under an extended-access research grant. Preregistrations, raw counts and analysis code: https://github.com/anulum/scpn-quantum-control
This preprint reports a preregistered dynamic-circuit quantum-control experiment comparing monitored feedback against matched open-loop control for a four-qubit Kuramoto--XY synchronisation payload. The experiment uses three system qubits, one monitor qubit, and three dynamic rounds to test feedback directly on IBM gate-model hardware. The primary ibm_kingston binary endpoint is negative: the monitored-feedback arm does not improve the selected target relative to the matched open-loop control. The same S1--S1f stack is then replicated on ibm_fez and ibm_marrakesh, where the primary endpoint is positive but direct-observable extensions show backend-dependent YYI and response structure. The contribution is therefore a hardware-control boundary result: it documents where the monitored-feedback policy fails, where it appears to improve the selected target, and why the result should not be interpreted as a simple backend-independent controller promotion. The record includes the source, bibliography, and rebuilt PDF.
H. Billah and M.M.H. Sarker contributed equally to this work. Interpreting a fixed quantum circuit's output as evidence of a hardware effect requires ruling out two things usually conflated with it: finite-sample fluctuation, and structure already present in the circuit's own noiseless output. Less commonly checked is a third: whether the reference circuit compared against is the one actually executed, once compiler-level qubit routing is accounted for. We execute a fixed 35-qubit, 243-gate diagnostic circuit on IBM Heron-family hardware (three runs, two backends) and show this third check is essential: the routed circuit submitted to hardware has different noiseless predictions than the logical circuit intended, for several qubits. Against the correct, routed-circuit reference, the aggregate deviation is significant in two of three runs, and four registers (0, 9, 14, 27) show a significant output-probability deviation in every run — though we distinguish a high-confidence subset, {0, 9, 27}, with tightly time-matched calibration, from qubit 14, included only on an exploratory basis given its calibration was retrieved roughly two weeks post-execution. Same-backend replicates correlate more strongly by the Pearson measure, though a rank-based (Spearman) test shows this gap does not survive at the level of register ordering, indicating substantial leverage from a small number of registers rather than a broadly robust pattern; these three executions also share a byte-identical payload and are not independent replications in the strictest sense. The mechanism is only partially resolved: independent single-qubit readout error and raw gate count are ruled out as complete explanations for most of these registers, but the simplest version of the leading hypothesis for the single most-affected register does not reproduce the observed cross-backend pattern even with live, backend-specific timing data. A second, structurally different circuit validated only in simulation calibrates the statistical procedure's behavior under one synthetic noise model; it does not itself establish generality to real hardware, and the specific register set found here should not be expected to generalize beyond this study. Note on scope: this is a methodology and case-study contribution centered on executed-circuit references for fixed-circuit diagnostics, not a characterization of IBM Heron hardware in general or a randomized-benchmarking experiment in the formal sense. Supporting data, the routed OpenQASM circuits, raw measurement counts, and analysis code for this study are available on request from the corresponding author. Affiliation: Sonicium Quantum Lab Ltd., Dhaka, Bangladesh.
Eight verified quantum computing jobs executed on IBM Quantum hardware (ibm_fez Heron R2, 156 qubits; ibm_torino Heron R1, 133 qubits) between January 27 and March 15, 2026. User ID: IBMid-692001DJRD. Experiments include: 1. Bell State Entanglement — 96.3% fidelity on ibm_fez Heron R2 (Concurrence C = 0.926, Tangle T = 0.858, 1,000 shots). Cross-platform benchmark: Heron R2 vs Heron R1 (+8.3 pp fidelity advantage, noise ratio 2.43×). 2. Reproducibility Test — Two independent runs of identical circuit (χ² = 2.70, p = 0.44, df = 3). H₀ not rejected: statistically indistinguishable results at 95% confidence. 3. BB84 Quantum Key Distribution — Full Alice/Eve/Bob protocol implementation. Alice baseline error 0.60% → Bob QBER 49.0% under eavesdropping (82× degradation). Experimental demonstration of the quantum no-cloning theorem. Control group design isolates eavesdropper signal from hardware noise baseline. 4. Variational Quantum Circuit (VQC) — 2-qubit circuit, 10 trained parameters with tied weights (θ₃ = θ₄), 8 CZ gates in 4 entangling layers. 4-qubit ansatz: Shannon entropy 3.885/4.000 bits (97.1%), ground-state bias confirmed (χ² = 300.94, p ≈ 0). 5. Quantum Random Number Generation (QRNG) — 8-bit outputs, 10/10 unique values per shot (range 16–254). Total: 39,010 quantum measurements across 8 jobs and 10 circuits. QPU time: 4.8 seconds. Job completion rate: 100%. All results decoded from raw IBM SamplerV2 BitArray binary archives (zlib + base64 + NumPy .npy pipeline). No simulations. Statistical validation applied throughout (Wilson 95% CIs, chi-squared tests). Stack: Qiskit Runtime SamplerV2 · QPY · OpenQASM 2.0 · Python · NumPy · SciPy Repository: https://github.com/dinohatibovicWhitepaper: https://dinohatibovic.github.io (Doc QAI-WP-2026-01-28-V4)
Qubit layout selection determining which physical qubits a logical circuit occupies on a superconducting processor is fundamentally a noise-field sampling problem. On IBM Heron r1 and Heron r2 devices, two-qubit gate error varies by nearly one order of magnitude (7– $9\times $ ) across qubit pairs on the same chip, causing measured fidelity differences up to 0.903 from layout choice alone. We introduce the Gate Noise Sensitivity Index (GNSI), a calibration-weighted linear combination of per-qubit readout error and per-edge two-qubit gate error, derived analytically as a first-order approximation of circuit fidelity under independent, heterogeneous noise channels. For 12 backend–circuit combinations on three IBM processors (133-qubit Heron r1 and 156-qubit Heron r2), GNSI scores are computed for the full pool of 1,320 computationally enumerated candidate layouts; the top-ranked (GNSI-BEST) and bottom-ranked (GNSI-WORST) layouts are then executed on hardware. GNSI-BEST ranks first by score in all 12 instances (Hit@1 = 100% within the enumerated candidate pool) and consistently achieves higher measured fidelity than GNSI-WORST, with Spearman rank correlation ρ=0.926±0.016 and statistically significant fidelity separation in 9 of 12 paired tests. Initial hardware comparisons on ibm_fez ( n=5 ) show GNSI-BEST matching or exceeding SABRE-selected fidelity. We further identify a depth-dependent regime transition: gate-error heterogeneity appears to govern ranking in shallow circuits (depth ≤15 ), while qubit-specific T1 variation may dominate for deeper circuits (depth ≥20 ). The analytic regime boundary d∗(b) , computable from calibration data alone, shows agreement within ±2 depth layers across all three backends in initial comparisons; GNSI-Extended incorporating the decoherence term receives an initial hardware comparison on two circuits, with full validation left to future work. These results suggest that layout-dependent fidelity variation may be governed by a calibration-predictable noise field, with direct implications for compiler design and noise-adaptive quantum circuit execution.