• This work proposes a practical initial layout method that utilizes matrix formulation to determine enhanced qubit assignments, without iterative optimization techniques and combinatorial search. • The proposed method computes the gradient of the objective function through a single matrix differentiation to obtain assignment suitability information between logical and physical qubits. • The gradient matrix encodes the interaction between physical-qubit centrality and logical-qubit connectivity, enabling direct mapping decisions that minimize error costs while satisfying hardware constraints. • Simulation results show that the proposed method improves computational efficiency while maintaining comparable execution reliability compared to existing qubit mapping methods. Qubit mapping is a crucial compilation process that assigns logical qubits from quantum circuits to physical qubits on quantum hardware, ensuring efficient and reliable execution on noisy intermediate-scale quantum (NISQ) computers. However, as the scale of quantum computers and circuit complexity increase, existing mapping approaches face significant computational complexity and suboptimal mapping quality. This work formulates the logic-to-physical qubit mapping problem as a matrix-form optimization problem to address scalability and computational efficiency challenges. The proposed method computes the gradient of the matrix-formulated problem through a single matrix differentiation and uses it as guidance to determine the enhanced qubit assignment, without the need for iterative combinatorial exploration and optimization solvers. Simulation results show that the proposed method achieves comparable execution reliability while significantly reducing the compilation time, even for multi-programming scenarios and large-scale quantum computers.
• This work proposes a practical initial layout method that utilizes matrix formulation to determine enhanced qubit assignments, without iterative optimization techniques and combinatorial search. • The proposed method computes the gradient of the objective function through a single matrix differentiation to obtain assignment suitability information between logical and physical qubits. • The gradient matrix encodes the interaction between physical-qubit centrality and logical-qubit connectivity, enabling direct mapping decisions that minimize error costs while satisfying hardware constraints. • Simulation results show that the proposed method improves computational efficiency while maintaining comparable execution reliability compared to existing qubit mapping methods. Qubit mapping is a crucial compilation process that assigns logical qubits from quantum circuits to physical qubits on quantum hardware, ensuring efficient and reliable execution on noisy intermediate-scale quantum (NISQ) computers. However, as the scale of quantum computers and circuit complexity increase, existing mapping approaches face significant computational complexity and suboptimal mapping quality. This work formulates the logic-to-physical qubit mapping problem as a matrix-form optimization problem to address scalability and computational efficiency challenges. The proposed method computes the gradient of the matrix-formulated problem through a single matrix differentiation and uses it as guidance to determine the enhanced qubit assignment, without the need for iterative combinatorial exploration and optimization solvers. Simulation results show that the proposed method achieves comparable execution reliability while significantly reducing the compilation time, even for multi-programming scenarios and large-scale quantum computers.
In recent years, the emergence of the Noisy Intermediate-Scale Quantum (NISQ) era has led to the development of a wide variety of quantum devices, marking a dynamic phase in the field of quantum computing. Despite these advancements, practical applications of quantum computers still face significant challenges, one of the most prominent being the limited connectivity between physical quantum bits (qubits). This limitation requires quantum circuits to be recompiled through layout synthesis before they can be executed on quantum devices. Layout synthesis determines the specific placement of quantum gates within the circuit on the physical hardware. When gates do not align with the connectivity constraints of the device, additional quantum gates must be inserted to remap the qubits, which can negatively affect the circuit’s efficiency and performance. To address this issue, the primary goal of this paper is to enhance the mapping process within layout synthesis, aiming to optimize both the layout and the circuit depth. Experimental results demonstrate that the proposed method effectively reduces the quantum circuit depth, outperforming other existing approaches in terms of efficiency.
Rapid progress in the physical implementation of quantum computers gave birth to multiple recent quantum machines implemented with superconducting technology. In these NISQ machines, each qubit is physically connected to a bounded number of neighbors. This limitation prevents most quantum programs from being directly executed on quantum devices. A compiler is required for converting a quantum program to a hardware-compliant circuit, in particular, making each two-qubit gate executable by mapping the two logical qubits to two physical qubits with a link between them. To solve this problem, existing studies focus on inserting SWAP gates to dynamically remap logical qubits to physical qubits. However, most of the schemes lack the consideration of time-optimality of generated quantum circuits, or are achieving time-optimality with certain constraints. In this work, we propose a theoretically time-optimal SWAP insertion scheme for the qubit mapping problem. Our model can also be extended to practical heuristic algorithms. We present exact analysis results by using our model for quantum programs with recurring execution patterns. We have for the first time discovered an optimal qubit mapping pattern for quantum fourier transformation (QFT) on 2D nearest neighbor architecture. We also present a scalable extension of our theoretical model that can be used to solve qubit mapping for large quantum circuits.
In the era of noisy intermediate-scale quantum (NISQ) computing, the limited connectivity between qubits is one of the common physical limitations faced by current quantum computing devices. Quantum circuit mapping methods transform quantum circuits into equivalent circuits that satisfy physical connectivity constraints by remapping logical qubits, making them executable. The optimization problem of quantum circuit mapping has NP-hard computational complexity, and existing heuristic mapping algorithms still have significant potential for optimization in terms of the number of quantum gates generated. To reduce the number of SWAP gates inserted during mapping, the solution space of the mapping problem is represented as a tree structure, and the mapping process is equivalent to traversing this tree structure. To effectively and efficiently complete the search process, a beam search framework (BSF) is proposed for solving quantum circuit mapping. By iteratively selecting, expanding, and making decisions, high-quality target circuits are generated. Experimental results show that this method can significantly reduce the number of inserted SWAP gates on medium to large circuits, achieving an average reduction of 44% compared to baseline methods, and is applicable to circuits of various sizes and complexities.
Quantum computing is a quickly growing field with great potential for future technology. Quantum computers in the current noisy intermediate-scale quantum (NISQ) era face two major limitations - qubit count and error vulnerability. Although quantum error correction (QEC) methods exist, they are not applicable to the current size of computers, requiring thousands of qubits, while current NISQ systems have hundreds at most. It is therefore imperative to improve the reliability of the circuits as much as possible to make them robust to the errors that will occur. One common approach is to adjust the compilation process of a circuit to create a final circuit with improved reliability. However, there are many decisions to be made when compiling that affect the final performance of the circuit, two of the most critical ones being the mapping of logical to physical qubits (the qubit allocation problem) and the movement of qubits to satisfy two-qubit gate adjacency requirements (the qubit routing problem). We focus on solving the qubit allocation problem and identifying initial layouts that reduce error. To identify these layouts, we combine reinforcement learning with a graph neural network (GNN)-based Q-network for analyzing both the connections and error rates of the graph-like backend of superconducting quantum computers to make mapping decisions, creating a Graph Neural Network Assisted Compilation (GNAQC) strategy. We provide both the circuit and the properties of the target backend as input to guide the decision-making process. We work with the IBM Qiskit API to compile and simulate our quantum circuits. We train the architecture using a set of four backends and six circuits and find that GNAQC generally outperforms pre-existing qubit allocation algorithms, increasing final relative output fidelity by roughly 12.7%.
Recent advancements in quantum computing have enabled practical use of quantum error detecting and correcting codes. However, current architectures and future proposals of quantum computer design suffer from limited qubit counts, necessitating the use of high-rate codes. Such codes, with their code parameters denoted as [[n,k,d]], have more than 1 logical qubit per code (i.e., k>1). This leads to reduced error tolerance of the code, since ⌈(d−1)/2⌉ errors on any of the n physical qubits can affect the logical state of all k logical qubits. Therefore, it becomes critical to optimally map the input qubits of a quantum circuit to these codes, in such a way that the circuit fidelity is maximized. \par However, the problem of mapping program qubits to logical qubits for high-rate codes has not been studied in prior work. A brute force search to find the optimal mapping is super exponential (scaling as O(n!), where n is the number of input qubits), making exhaustive search infeasible past a small number of qubits. We propose a framework that addresses this problem on two fronts: (1) for any given mapping, it performs logical-to-physical compilation that translates input gates into efficiently encoded implementations utilizing Hadamard commutation and gate merging; and (2) it quickly searches the space of possible mappings through a merge-optimizing, noise-biased packing heuristic that identifies high-performing qubit assignments without exhaustive enumeration. To the best of our knowledge, our compiler is the first work to explore mapping and compilation for high-rate codes. Across 71 benchmark circuits, we reduce circuit depth by 34%, gate counts by up to 31% and 17% for one-qubit and two-qubit gates, and improve total variation distance by 1.75×, with logical selection rate improvements averaging 86% relative to naive compilation.
The qubit mapping approach serves to transform a quantum logical circuit (LC) into a physical one that satisfies the connectivity constraints imposed by the noisy intermediate-scale quantum (NISQ) devices. The quality of the physical circuit generated by a mapping approach depends largely on the initial mapping, which specifies the correspondence between the qubits in the LC and the qubits on the NISQ device. There are a total ofn!different initial mappings for a qubit mapping problem withnqubits, and among them, there is at least one initial mapping corresponding to the smallest physical circuit that this mapping approach can output. Finding such an initial mapping is very important for reliable computations on the NISQ device. To this end, we propose an iterated local search framework as well as a heuristic circuit mapper. In this framework, we perform multiple local searches on the space of initial mappings, and during each local search, several promising neighborhoods of the current initial mapping are generated and evaluated by invoking the circuit mapper in a forward or a backward manner. This framework provides a way for the qubit mapping approach to find the best physical circuit that it can produce, allowing it to trade time for circuit quality, which is necessary in the NISQ era. The experimental results demonstrate the stability, scalability, and effectiveness of this approach in reducing the number of additional gates. Moreover, although this approach is a multipass circuit mapping process, it can generate a good-quality physical circuit within half an hour, even for the circuit with more than 10 000 gates.