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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

An Iterated Local Search Methodology for the Qubit Mapping Problem

Pengcheng Zhu, Shiguang Feng, Zhijin Guan

Published Sep 13, 2021• 20 citations
Publisher

Abstract

The qubit mapping approach serves to transform a quantum logical circuit (LC) into a physical one that satisfies the connectivity constraints imposed by the noisy intermediate-scale quantum (NISQ) devices. The quality of the physical circuit generated by a mapping approach depends largely on the initial mapping, which specifies the correspondence between the qubits in the LC and the qubits on the NISQ device. There are a total of$n!$different initial mappings for a qubit mapping problem with$n$qubits, and among them, there is at least one initial mapping corresponding to the smallest physical circuit that this mapping approach can output. Finding such an initial mapping is very important for reliable computations on the NISQ device. To this end, we propose an iterated local search framework as well as a heuristic circuit mapper. In this framework, we perform multiple local searches on the space of initial mappings, and during each local search, several promising neighborhoods of the current initial mapping are generated and evaluated by invoking the circuit mapper in a forward or a backward manner. This framework provides a way for the qubit mapping approach to find the best physical circuit that it can produce, allowing it to trade time for circuit quality, which is necessary in the NISQ era. The experimental results demonstrate the stability, scalability, and effectiveness of this approach in reducing the number of additional gates. Moreover, although this approach is a multipass circuit mapping process, it can generate a good-quality physical circuit within half an hour, even for the circuit with more than 10 000 gates.

DOI
10.1109/tcad.2021.3112143

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The qubit mapping approach serves to transform a quantum logical circuit (LC) into a physical one that satisfies the connectivity constraints imposed by the noisy intermediate-scale quantum (NISQ) devices. The quality of the physical circuit generated by a mapping approach depends largely on the initial mapping, which specifies the correspondence between the qubits in the LC and the qubits on the NISQ device. There are a total ofn!n!n!different initial mappings for a qubit mapping problem withnnnqubits, and among them, there is at least one initial mapping corresponding to the smallest physical circuit that this mapping approach can output. Finding such an initial mapping is very important for reliable computations on the NISQ device. To this end, we propose an iterated local search framework as well as a heuristic circuit mapper. In this framework, we perform multiple local searches on the space of initial mappings, and during each local search, several promising neighborhoods of the current initial mapping are generated and evaluated by invoking the circuit mapper in a forward or a backward manner. This framework provides a way for the qubit mapping approach to find the best physical circuit that it can produce, allowing it to trade time for circuit quality, which is necessary in the NISQ era. The experimental results demonstrate the stability, scalability, and effectiveness of this approach in reducing the number of additional gates. Moreover, although this approach is a multipass circuit mapping process, it can generate a good-quality physical circuit within half an hour, even for the circuit with more than 10 000 gates.
In the era of noisy intermediate-scale quantum (NISQ) computing, the limited connectivity between qubits is one of the common physical limitations faced by current quantum computing devices. Quantum circuit mapping methods transform quantum circuits into equivalent circuits that satisfy physical connectivity constraints by remapping logical qubits, making them executable. The optimization problem of quantum circuit mapping has NP-hard computational complexity, and existing heuristic mapping algorithms still have significant potential for optimization in terms of the number of quantum gates generated. To reduce the number of SWAP gates inserted during mapping, the solution space of the mapping problem is represented as a tree structure, and the mapping process is equivalent to traversing this tree structure. To effectively and efficiently complete the search process, a beam search framework (BSF) is proposed for solving quantum circuit mapping. By iteratively selecting, expanding, and making decisions, high-quality target circuits are generated. Experimental results show that this method can significantly reduce the number of inserted SWAP gates on medium to large circuits, achieving an average reduction of 44% compared to baseline methods, and is applicable to circuits of various sizes and complexities.
Quantum circuit mapping (QCM) is a crucial preprocessing step for executing a logical circuit (LC) on noisy intermediate-scale quantum (NISQ) devices. Balancing the introduction of extra gates and the efficiency of preprocessing poses a significant challenge for the mapping process. To address this challenge, we propose the mutual-influence-aware (MIA) heuristic method by integrating an initial mapping search framework, an initial mapping generator, and a heuristic circuit mapper. Initially, the framework utilizes the generator to obtain a favorable starting point for the initial mapping search. With this starting point, the search process can efficiently discover a promising initial mapping within a few bidirectional iterations. The circuit mapper considers mutual influences of SWAP gates and is invoked once per iteration. Ultimately, the best result from all iterations is considered the QCM outcome. The experimental results on extensive benchmark circuits demonstrate that, compared to the iterated local search (ILS) method, which represents the current state-of-the-art, our MIA method introduces a similar number of extra gates while achieving nearly 95 times faster execution.
In the era of noisy intermediate-scale quantum (NISQ), a quantum logical circuit must undergo certain compilation before it can be used on a NISQ device, subject to connectivity constraints posed by NISQ devices. During compilation, numerous auxiliary quantum gates are inserted, but a circuit with too many is unreliable, necessitating gate minimization. This requirement gives rise to the qubit mapping problem (QMP), an NP-hard optimization problem that is critical in quantum computing. This work proposes a novel and effective local search algorithm dubbedEffectiveQM. First,EffectiveQMproposes a new mode-aware search strategy to alleviate the challenge of being trapped in local optima, where local search typically suffers. Moreover,EffectiveQMintroduces a novel potential-guided scoring function, which can thoroughly quantify the actual benefit brought by an operation of inserting auxiliary gates. By incorporating the potential-guided scoring function,EffectiveQMcan effectively determine the appropriate operation to be performed. Extensive experiments on a diverse collection of logical circuits and 6 NISQ devices demonstrate thatEffectiveQMcan generate physical circuits with significantly fewer inserted auxiliary gates than current state-of-the-art QMP algorithms, indicating thatEffectiveQMgreatly advances the state of the art in QMP solving.
The noisy intermediate-scale quantum (NISQ) computer significantly advances quantum computing technology. Due to the physical connectivity constraints of the NISQ device, its induced qubit mapping problem becomes more challenging. Recent works employ heuristics to achieve promising outcomes. However, they are limited to using only one type of center for graph matching, and their exhaustive traversal of the coupling graph results in high computation time. This paper strategically generates specific subgraphs during the initial mapping stage to reduce the solution space for the coupling graph. Then, we employ a bidirectional graph isomorphism search to improve initial mapping. In the main mapping stage, we develop an efficient search algorithm to minimize the number of inserted gates. Experimental results show that our method significantly outperforms the state-of-the-art work in reducing the number of inserted CNOT gates by 13.22% and the runtime by 19.61%.
In the past few years, several quantum computers realized by the noisy intermediate-scale quantum (NISQ) technology have been released. However, there exists a significant limitation to using such computers, i.e., the connectivity constraint between physical qubits. To perform a 2-qubit quantum operation on such NISQ computers, its two logical qubits have to be mapped to a pair of physical qubits that satisfy the connectivity constraint. This mapping procedure requires additional operations to be introduced into the original quantum circuit, reducing its fidelity. Therefore, it is of great significance to design an algorithm that is able to complete the mapping task with minimal additional operations. In this article, we propose an efficient algorithm to solve this problem. Our algorithm consists of two core components, an expansion-from-center scheme to determine the initial mapping and a SWAP-based heuristic search algorithm to update the mapping. We introduce the maximum consecutive positive effect of a SWAP operation as the heuristic cost function, allowing our search algorithm to look ahead dynamically. Our algorithm is evaluated on IBM Q 20. The experimental results show that our algorithm can complete the mapping task in a very short time even for large-scale benchmarks with hundreds of thousands of operations, and outperforms the state-of-the-art in terms of the number of additional operations for most benchmarks considered.
This paper presents an efficient qubit-mapping method that redesigns a quantum circuit to overcome the limitations of qubit connectivity. We propose a recursive graph-isomorphism search to generate the scalable initial mapping. In the main mapping, we use an adaptive look-ahead window search to resolve the connectivity constraint within a short runtime. Compared with the state-of-the-art method [15], our proposed method reduced the number of additional gates by 23% on average and the runtime by 68% for the three largest benchmark circuits. Furthermore, our method improved circuit stability by reducing the circuit depth and thus can be a step forward towards fault tolerance.